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PA-RISC Chipsets

ASP

Used in

ASP is the the chipset used in all older PA-RISC workstations, still being a classical chipset, it includes several different chips to provide the I/O subsystem. It includes several modules from 3rd party vendors to complete the system. The ASP2 chipset, used in the 735 and 755 workstations, offers some small feature improvements (faster SCSI and addditional FDDI networking).

Features

References

Hardball I/O Subsystem, External Reference Specification
Hewlett-Packard Company (September 1991, Version 1.1).

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Astro

Used in

Newer workstations and servers use the Astro chip for memory and I/O management. It includes most of the functions on a single die, requiring only few additional peripheral ASICs to interface and drive the specific buses.

Astro attaches to three different buses and is the central part of the chipset:

  1. Processor system bus — Runway for (theoretically) up to two PA-8x000 processors with a max. clock of 120MHz and max. bandwidth of 1.9GB/s
  2. Memory bus with a max. bandwidth of 1.9GB/s
  3. I/O system buses made up from up to eight single I/O links (ropes) which attach to individual PCI bridges — in most cases Elroy chips which convert each one or two I/O links into a PCI bus

There are several different variants of Astro.

Features

References

Astro External Reference Specification Introduction
Astro External Reference Specification Error Handling
Astro External Reference Specification R2I Operations
Astro External Reference Specification Register Map
Astro External Reference Specification Runway Interface
Astro External Reference Specification Memory Map
Hewlett-Packard Company (February 2000, Revision 1.2).

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Dino/Cujo

1FC3-0004

Used in

Dino is the GSC-to-PCI bridge found in most older PCI-based PA-RISC workstations. The GSC and PCI bus do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions.

Cujo is a Dino bridge with a 64-bit datapath.

Features

References

DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge
Hewlett-Packard Company (February 1997, Revision 3.0).
Dino 3.1 (1FC3-0004) Errata Listing
Hewlett-Packard Company (September 1997).

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Elroy

Used in

Elroy is the chip used to attach a PCI bus to the system and I/O buses in the various newer PA-RISC systems. Each Elroy chip attaches one PCI bus to one or more of the I/O system’s I/O channels — ropes. Common configurations are one I/O link (about 250MB/s) for one Turbo PCI bus (can have multiple slots or attach multiple I/O devices) or two I/O links (about 500MB/s) for one Twin Turbo bus.

Elroy is also called LBA one some of the newer systems.

Features

References

Elroy ERS (External Reference Specification) — Ropes to PCI Bridge Chip
Hewlett-Packard Company (January 2000, Revision A (1.4)).

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LASI

1FT1-0002, 1FU2-0002

Used in

Designed for and firstly used in the 712 series workstations the LASI I/O chip was similarly designed for cost-reduction. One of the major objectives of the 712 I/O subsystem was to provide similar or equal functionality and performance like other 700 series systems (e.g. 720, 730, 715 Scorpio) at a significantly reduced manufacturing cost. The design team finally concluded that integrating major parts of the I/O subsystem into one large VLSI chip would reduce the fabrication cost significantly, as required. The majority of circuitry in LASI is consumed by the two most important parts: LAN and SCSI (therefore LAN SCSI). Both of these designs were purchased from third party companies (NCR and Intel) and integrated as so-called mega-cells in the VLSI chip. The other I/O functions originate from HP internal standard cell designs, some of whom were leveraged from previous HP ASIC designs and some designed specifically for LASI.

Features

Besides this chip only very few parts are needed to build a complete system: CPU, cache, RAM and a graphics adaptor. It is furthermore possible to use up to four LASI chip on a single GSC bus.
The LASI chip was designed in a 0.8u CMOS process and is 13.2 x 12.0 mm2 in size. It contains 520,000 FETs and is packaged in a 240-pin MQUAD package. It consumes about 3W when operating an 40MHz.

References

712 I/O Subsystem ERS (External Reference Specification) — LASI ERS
Hewlett-Packard Company (February 1993, Revision 1.1).
An I/O System on a Chip
Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal).

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Cell-based (Superdome)

Used in

The Superdome and various smaller systems from HP used a cell-based system architecture or Central Electronics Complex (CEC) which was based on interconnecting individual system/processor cells via central crossbars. The cell boards were seated in the backplane of the system, which provided the cell-to-cell links and I/O functionality.

  1. Cell controller (CC): the central chipset and crossbar of these systems. One sits at the centre of each cell board for a maximum of two in the complete system. The CCs provide links for:
    • Up to four Processors (8.0GB/s)
    • Up to two Memory banks (4.0GB/s peak)
    • I/O via SBA (cell to I/O communication is 2.0GB/s peak)
    • PDH (processor dependent hardware) and firmware/flash etc.
    • Second cell via XBC (cell-to-cell communication is 8.0GB/s peak)
  2. Master I/O controller (SBA): the central I/O part of the main chipset, normally one SBA is reserver for each one cell/CC but located on the (I/O) backplane. Each SBA provides sixteen 12-bit links (ropes) — the links/ropes from the SBAs connect to slave I/O controllers (LBAs) which in turn connect the PCI I/O slots and I/O subsystems
  3. Core I/O: provides the standard I/O functions for the system. Made up of cards or card sets, which plug into PCI or special slots and provide third-party I/O functions. Distinct cards were availaible/possible: MP/SCSI card and LAN/SCSI, among others. These cards contain a variety of I/O chips, including Ultra160 SCSI, Ultra2-Wide SCSI, Gigabit Ethernet LAN. Ethernet for management LAN, serial ports for management and console, etc.

Other parts of the chipset are made up from already known components:

References

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Stretch

Used in

Stretch is the chipset or Central Electronics Complex (CEC) used in a very small range of systems. It basically consists of four main components, which build the backbone of the (Runway-based PA-8x00) processor/memory and I/O system — one central memory controller which connects all system buses together; Runway ports for attachment of processors to the system bus; I/O controllers which attach the I/O subsystem to the system bus; PCI bridges, which convert the I/O subsystem’s links into PCI buses:

  1. Prelude SMC memory controller is the central part of the system, it connects the main memory to two system buses (one on each side), to which each one IKE I/O controller and one or more DEW Runway ports (for each two CPUs) attach (Prelude is also called Very Low Latency Memory Controller)
  2. DEW Runway ports/converters convert the Prelude’s system bus(es) (which in fact is an Itanium/Merced bus) into Runway buses for the various CPUs — each two CPUs share one DEW port converter (CPUs from the PA-8500 upwards supported). Common configurations include 1-4 DEWs for up to eight processors.
  3. IKE I/O controllers attach each to the system bus. Common configurations are one IKE for each of the two system buses (one on each side). IKEs then connect to the varios PCI bridges.
  4. Elroy PCI bridges (LBAs) which convert the I/O channels from the IKE I/O controllers into PCI buses, to which the PCI slots and core I/O functions attach. Up to 14 Elroys were used in actual systems.

Features

References

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