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PA-RISC Chipsets

Overview

Most HP PA-RISC computers used proprietary HP chipsets and system designs. Early 32-bit workstations (HP 9000/700) and servers HP 9000/800) from the 1990s used different chipsets; later on, the system platforms of workstations and servers moved closer and used the same chipsets.

Most chipsets were tied to specific bus architectures but were sometimes used in different generations of systems.

Chipsets used in PA-RISC computers overview
Type Part of Interface Usage
ASP VSC, GSC Chipset
LASI GSC Chipset
Stretch Various Chipset
Cell System, I/O ropes Chipset
zx1 Various Chipset
Wax (LASI) GSC Bus bridge (EISA, HIL, HP-IB)
Dino GSC Bus bridge (PCI)
Cujo GSC Bus bridge (PCI-64)
Elroy I/O ropes Bus bridge (PCI-64)
Mercury zx1 I/O ropes Bus bridge (PCI-64/AGP)
U2 MMC/SMC Runway Bus bridge (GSC+)
UTurn MMC/SMC Runway Bus bridge (GSC2)
SIU/SPI SMB CPU bridge
Viper ASP PBus, VSC CPU bridge, memory controller
MIOC CPU on-CPU, GSC CPU bridge, memory controller
DEW Stretch Runway, Itanium CPU bridge
MMC/SMC U2/UTurn Runway Memory controller
Prelude Stretch Itanium Memory controller
Astro Runway, I/O ropes I/O and memory controller
Pluto zx1 Itanium-2, I/O ropes I/O and memory controller
IKE Stretch Itanium, I/O ropes I/O controller

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ASP

ASP is the chipset used in many older 32-bit PA-RISC workstations with SGC bus and PA-7000 and PA-7100 processors. Being an integrated chipset, ASP includes separate chips to provide the I/O subsystem and contains several modules from third-party vendors.

There are two variants of ASP:

  1. Coral or Cobra I/O subsystem, the original ASP
  2. Hardball an improved ASP2 variant with fast/wide SCSI and FDDI networking, apparently used only on the 735/755 workstations

ASP normally was not used in multiprocessor systems, although the PA-7100 processors were SMP-capable.

Features

ASP EISA bridges

Most systems with ASP chipsets feature a separate EISA bus, implemented with the Intel 82350 chipset (82352 EISA buffer, 82357 peripheral and 82358 controller). The EISA adapter is not integrated into of ASP but listed here since it was only used with ASP systems.

ASP2 features (additional)

Used in

References

  1. Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal) pp. 6-11
  2. VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) Craig A. Gleason (August 1992: Hewlett-Packard Journal) pp. 12-22
  3. High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) Craig Fink et al (August 1992: Hewlett-Packard Journal) pp. 56-63
  4. Hardball I/O Subsystem, External Reference Specification (.pdf) Hewlett-Packard Company (September 1991, Version 1.1)
  5. The EISA standard for the HP 9000 Series 700 workstations (.pdf) Vicente Cavanna and Christopher S. Liu (December 1992, Hewlett-Packard Journal) pp. 78

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LASI

LASI is an highly integrated chipset primarily designed for cost-reduction while still providing most I/O functions. It was used as the main controller in most PA-7100LC and PA-7300LC systems, while later 64-bit PA-8x00 systems used LASI for complementary I/O functions.

The primary cost reductions were achieved by integrating the major I/O subsystems into a single chip. Large parts of the LASI chip are consumed by the LAN and SCSI controller (LAN SCSI), which both being third party designs (NCR and Intel). Other I/O functions are HP-internal standard designs, some taken over from previous HP ASICs and some designed specifically for LASI. The memory and I/O controller was not contained in the chipset but provided by the on-CPU MIOC on the PA-7100LC and PA-7300LC processors or the main chipset controller in the PA-8x00 systems.

Features

Used in

References

  1. 712 I/O Subsystem ERS (External Reference Specification) — LASI ERS Hewlett-Packard Company (February 1993, Revision 1.1)
  2. An I/O System on a Chip Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)

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Stretch

Stretch is the chipset used in a small range of systems, based on 64-bit PA-RISC processors but with Itanium (Merced) main buses. It consists of four main components that are improved previous designs.

  1. Prelude memory controller is the central part of the system that connects the main memory to two system buses.
  2. DEW Runway ports/converters convert the system buses into Runway buses for the CPUs — each pair of two CPUs share one DEW. Common configurations include 1-4 DEWs for up to eight processors. Processor types from the PA-8500 upwards are supported.
  3. IKE I/O controllers attach PCI bridges via I/O links to the system bus. Common configurations are one IKE for each of the two system buses. IKEs then connect to the various PCI bridges.
  4. Elroy PCI bridges convert the I/O channels from IKE I/O controllers into PCI buses, which provide PCI slots and core functions.

» For illustration view a system-level description of the N4000 server (Stretch-based).

Used in

References

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Cell

The Superdome and various smaller systems from HP used a cell-based system architecture or Central Electronics Complex (CEC) which was based on interconnecting individual system/processor cells via central crossbars. The cell boards were seated in the backplane of the system, which provided the cell-to-cell links and I/O functionality.

  1. Cell controller (CC): the central chipset and crossbar of these systems. One sits at the centre of each cell board for a maximum of two in the complete system. The CCs provide links for:
    • Up to four Processors (8.0 GB/s)
    • Up to two Memory banks (4.0 GB/s peak)
    • I/O via SBA (cell to I/O communication is 2.0 GB/s peak)
    • PDH (processor dependent hardware) and firmware/flash etc.
    • Second cell via XBC (cell-to-cell communication is 8.0 GB/s peak)
  2. Master I/O controller (SBA): the central I/O part of the main chipset, with one SBA reserved for each cell/CC, located on the (I/O) backplane. Each SBA provides sixteen 12-bit links (ropes) — the links/ropes from the SBAs connect to slave I/O controllers (LBAs) which in turn connect the PCI I/O slots and I/O subsystems
  3. Core I/O: provides the standard I/O functions for the system. Made up of cards or card sets, which plug into PCI or special slots and provide third-party I/O functions. Distinct cards were availaible/possible: MP/SCSI card and LAN/SCSI, among others. These cards contain a variety of I/O chips, including Ultra160 SCSI, Ultra2-Wide SCSI, Gigabit Ethernet LAN. Ethernet for management LAN, serial ports for management and console, etc.

Other parts of the chipset are made up from already known components:

Used in

References

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zx1

The zx1 chipset was designed for HP Itanium-based systems but used in some of the later PA-RISC based servers as well. It consists of two purpose-built main parts that connect the processor, memory and I/O to the Itanium system main buses:

  1. Pluto zx1 memory and I/O controller (MIO) is the main chipset controller and connects the three central system buses:
    1. Processor bus
    2. Two independent memory buses
    3. I/O channels (I/O ropes)
    Pluto also contains memory and cache controllers. Part of the memory subsystems are sometimes the zx1 SMEs (scalable memory expanders) that increase memory capacity and data rate (through multplexing)
  2. Mercury zx1 I/O adapters (IOAs) connect PCI-X/AGP slots and I/O devices to Pluto

The rest of the I/O chipset is made up of standard third-party I/O parts, such as SCSI controllers, Ethernet devices etc.

Used in

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Wax

Wax is a secondary I/O controller complimentary to the LASI chipset. It implements various secondary I/O functions and acts as a I/O bus to GSC adapter for different external buses as EISA, HP-HIL and HP-IB. Most systems use it to complement LASI with other required I/O functions that were previously implented in diverse I/O ASICs. It is implemented in the same process and package as LASI.

Features

Used in

References

  1. External Reference Specification (ERS) for the Wax I/O ASIC Hewlett-Packard Company (May 1993, version 1.0 redacted)

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Dino/Cujo

Dino is the GSC to PCI bridge found in many older PCI PA-RISC workstations. The GSC and PCI buses do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions.

Cujo is a Dino bridge with 64-bit PCI.

Features

Used in

References

  1. DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge Hewlett-Packard Company (February 1997, Revision 3.0)
  2. Dino 3.1 (1FC3-0004) Errata Listing Hewlett-Packard Company (September 1997)

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Elroy

Elroy is a PCI bus bridge that attaches one PCI bus to one or more I/O ropes. Common configurations are one 250 MB/s I/O rope for one Turbo PCI bus (can have multiple slots or attach multiple I/O devices) or two I/O links (about 500 MB/s) for one Twin Turbo bus.

Elroy was often used with the Astro memory and I/O controller.

Features

Used in

References

  1. Elroy ERS (External Reference Specification) — Ropes to PCI Bridge Chip Hewlett-Packard Company (January 2000, Revision A (1.4))

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Mercury (zx1)

Mercury is a PCI/AGP bridge for systems based on I/O ropes. It is part of the zx1 chipset used on Itanium systems (called zx1 I/O adapter), and based on the Elroy PCI bridge, extending it for AGP devices and faster I/O ropes. Most systems use several Mercury chips to attach PCI/AGP buses to the multiple I/O ropes. Each Mercury attaches one PCI or AGP bus to up to four 500 MB/s I/O ropes.

Mercury is most often used together with the Pluto I/O and memory controller of the zx1 chipset.

Features

Used in

References

  1. HP zx1 ioa ERS External Reference Specification Ropes to AGP/PCI/PCI-X Bridge (.pdf) Hewlett-Packard Company (April 2003, Revision 3.2)

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U2/UTurn

U2 and UTurn I/O adapters (IOAs) attach I/O devices and buses (GSC) to the Runway CPU bus on systems with PA-7200, PA-8000 and PA-8200 processors. On the I/O side they provide two GSC (HSC) buses to which other I/O chips and bridges or chipsets attach.

U2 is the variant for PA-7200 systems while all later systems use the UTurn follow-on.

Details

Used in

References

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SIU/SPI

The first PA-RISC processors (1.0) used external support chips to attach the CPU to memory and I/O. This functionality was in later processors integrated into single chips and then moved to the CPU altogether.

The bus setup and structure is similar on NS-1, NS-2 and PCX processors with the SMB CPU attachment but uses different support chips.

NS-1:

NS-2:

PCX:

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Viper

Viper is the memory and I/O controller (MIOC) on systems with PA-7000 and PA-7100 processors. The chip is similar on both, and sometimes counted into the ASP I/O chipset.

Viper interfaces with PBus to the processor and VSC to the system main bus. It handles all memory and I/O traffic between the processor and the rest of the system.

Bus attachments

Details

Used in

References

  1. Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
  2. VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)
  3. High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) pp. 56-63 Craig Fink et al (August 1992: Hewlett-Packard Journal)

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Memory and I/O Controller (MIOC)

The Memory and I/O Controller in the PA-7100LC and PA-7300LC processor integrates DRAM/cache and I/O controller onto the processor die. It is similar on both CPUs, with the PA-7300LC MIOC having wider data paths to L2 cache and RAM and supporting the advanced GSC+ bus over the older GSC.

The integrated memory controller requires only buffers and DRAM modules to build up the complete memory subsystem. The PA-7300LC memory controller includes a Second Level Cache Controller (SLC), which provides an optional L2 cache, ranging from 32 KB to 8 MB. It shares the data bus with the DRAM subsystem, so it has the same width (64/128-bit) and same optional SEDC error control.

Details

Used in

References

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DEW (Stretch)

DEW is the Runway CPU bridge for systems based on the Stretch chipset. It attaches the Runway-based PA-8500, PA-8600 and PA-8700 CPUs to the Itanum-based system man buses. Each pair of two CPUs share one DEW port converter. Common configurations include one to four DEWs for up to eight processors.

Details

Used in

References

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MMC/SMC

Most systems with a PA-7200, PA-8000 or PA-8200 processor use a combination of the MMC and SMC memory controllers to attach the main system memory to the Runway processor bus. The I/O is controlled by the U2/UTurn I/O adapters on the same Runway bus.

Details

Used in

References

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Prelude (Stretch)

Prelude is the memory controller of systems with the Stretch chipset and connects the main memory via four memory buses to two system buses. The main buses are in fact Itanium/Merced buses in preparation of the HP shift from PA-RISC to Itanium. Systems with Stretch theoretically could have been upgraded to Itanium processors, which however never realized.

Details

Used in

References

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Astro

Newer workstations and servers, based on PA-8500, PA8600 and 8700 processors, use the Astro chip for memory and I/O management (IOMMU). Pluto is the successor of Astro for Itanium-2 processors and buses; it works very similar.

Astro attaches to three different buses and is the central part of the chipset:

  1. Processor system bus — Runway+/Runway DDR for up to two PA-8x00 processors with a maximum lock of 125 MHz and peak bandwidth of about 2.0 GB/s with DDR
  2. Memory bus with a peak bandwidth of 2.0 GB/s at maximum clock of 125 MHz (the memory bus is a variant of Runway)
  3. I/O system buses made up from up to eight single I/O links (ropes) which attach to individual PCI bridges (mostly Elroy chips) which convert each one or two I/O links into a PCI bus. Peak aggregate I/O bandwidth is 2.0 GB/s

Features

Used in

References

  1. Astro External Reference Specification Introduction
    Astro External Reference Specification Error Handling
    Astro External Reference Specification R2I Operations
    Astro External Reference Specification Register Map
    Astro External Reference Specification Runway Interface
    Astro External Reference Specification Memory Map
    Hewlett-Packard Company (February 2000, Revision 1.2)

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Pluto (zx1)

Many of the Itanium-based HP workstations and servers use the Pluto I/O and memory controller as part of the zx1 chipset. Pluto is based on the Astro IOMMU, extending it for Itanium-2 processors and bus interfaces, DDR memory and faster I/O links.

Pluto is a IOMMU and attaches to three different buses, acting as central crossbar:

  1. Processor bus: Itanium-2 processor bus for one to four CPUs. The bus runs at maximum of 200 MHz with a width of 128-bits and has ECC-protection, for up to 6.4 GB/s data rate.
  2. Two memory bus with a peak bandwidth of aggregated 8.0 GB/s at maximum clock of 266 MHz DDR. Can be extended with the zx1 SME for more memory and higher peak datarate of 12.8 GB/s
  3. I/O system based on eight separate 500 MB/s I/O links (ropes) which attach to individual PCI, PCI-X or AGP bridges. Peak aggregate I/O bandwidth is 3.2 GB/s

Features

Used in

References

  1. zx1 mio (Memory and I/O) External Reference Specification Hewlett-Packard Company (March 2003, Revision 1.0)

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IKE (Stretch)

IKE is the I/O controller on systems with the Stretch chipset. The central memory controller provides one or two system buses, to which CPUs and I/O attach. Each system bus has one IKE I/O controller that connects to several slave I/O controllers (Elroy PCI bridges), which in turn provide PCI buses. The connection between IKE and each slave I/O controller is one or two 12-byte wide I/O links (I/O ropes). I/O channels can be combined into twin I/O channels for so-called Twin-Turbo PCI slots/buses.

Details

Used in

References

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