PA-RISC Chipsets
Overview
Most HP PA-RISC computers used proprietary HP chipsets and system designs. Early 32-bit workstations (HP 9000/700) and servers HP 9000/800) from the 1990s used different chipsets; later on, the system platforms of workstations and servers moved closer and used the same chipsets.
Most chipsets were tied to specific bus architectures but were sometimes used in different generations of systems.
| Type | Part of | Interface | Usage |
|---|---|---|---|
| ASP | VSC, GSC | Chipset | |
| LASI | GSC | Chipset | |
| Stretch | Various | Chipset | |
| Cell | System, I/O ropes | Chipset | |
| zx1 | Various | Chipset | |
| Wax | (LASI) | GSC | Bus bridge (EISA, HIL, HP-IB) |
| Dino | GSC | Bus bridge (PCI) | |
| Cujo | GSC | Bus bridge (PCI-64) | |
| Elroy | I/O ropes | Bus bridge (PCI-64) | |
| Mercury | zx1 | I/O ropes | Bus bridge (PCI-64/AGP) |
| U2 | MMC/SMC | Runway | Bus bridge (GSC+) |
| UTurn | MMC/SMC | Runway | Bus bridge (GSC2) |
| SIU/SPI | SMB | CPU bridge | |
| Viper | ASP | PBus, VSC | CPU bridge, memory controller |
| MIOC | CPU | on-CPU, GSC | CPU bridge, memory controller |
| DEW | Stretch | Runway, Itanium | CPU bridge |
| MMC/SMC | U2/UTurn | Runway | Memory controller |
| Prelude | Stretch | Itanium | Memory controller |
| Astro | Runway, I/O ropes | I/O and memory controller | |
| Pluto | zx1 | Itanium-2, I/O ropes | I/O and memory controller |
| IKE | Stretch | Itanium, I/O ropes | I/O controller |
ASP
ASP is the chipset used in many older 32-bit PA-RISC workstations with SGC bus and PA-7000 and PA-7100 processors. Being an integrated chipset, ASP includes separate chips to provide the I/O subsystem and contains several modules from third-party vendors.
There are two variants of ASP:
Coral
orCobra I/O subsystem,
the original ASPHardball
an improved ASP2 variant with fast/wide SCSI and FDDI networking, apparently used only on the 735/755 workstations
ASP normally was not used in multiprocessor systems, although the PA-7100 processors were SMP-capable.
Features
- VSC interface to system main bus, 32-bit, to the Viper memory controller
- GSC interface to main I/O bus (also sometimes called
SGC
) - (Viper memory controller — sometimes counted into the ASP chipset and sometimes part of the CPU)
- NCR 53C700 8-bit Narrow single-ended SCSI-2
- Intel 82596DX 10 Mbit Ethernet controller
- Intel 82501AD Ethernet transceiver, media auto-selection
- Domain keyboard controller (not implemented on ASP2)
- WD 16C552 parallel
- NS 16550A compatible serial (three ports on ASP, two ports on ASP2)
- 512 KB EPROM — the Boot ROM
- 8 KB EEPROM for storing system configuration status etc.
- Intel 8042 microprocessor controlling:
- Battery backed RTC
- System & user timers
- Audio generator
- HP-HIL interface
- Frontpanel system status LEDs
- 25-33 MHz chipset clock frequency
- 160-pin QFP chip
ASP EISA bridges
Most systems with ASP chipsets feature a separate EISA bus, implemented with the Intel 82350 chipset (82352 EISA buffer, 82357 peripheral and 82358 controller). The EISA adapter is not integrated into of ASP but listed here since it was only used with ASP systems.
ASP2 features (additional)
- NCR 53C720 16-bit Fast-Wide differential SCSI-2
- ASP2: AMD Formac Plus Am79C830 FDDI controller
- ASP2: Stereo/CD quality audio
- Two 32-bit device data buses (variant of GSC bus)
- One bus attaches to LAN an FDDI
- One bus attaches to the two SCSI controllers, audio and via an 8-bit bus converter to the other I/O devices (serial, parallel, etc.)
- ASP2 consists of two separate chips:
- Shortstop: main data attachment to the VSC system main bus and Viper memory controller with 33 MHz clock speed, produced in 0.8µ (micron) in CMOS (CMOS26B) packaged in 160-pin PLCC
- Cutoff: the main address controller with 33 MHz clock speed, produced in 0.8µ (micron) in CMOS (CMOS26B) packaged in 240-pin PQFP
Used in
References
- Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal) pp. 6-11
- VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) Craig A. Gleason (August 1992: Hewlett-Packard Journal) pp. 12-22
- High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) Craig Fink et al (August 1992: Hewlett-Packard Journal) pp. 56-63
- Hardball I/O Subsystem, External Reference Specification (.pdf) Hewlett-Packard Company (September 1991, Version 1.1)
- The EISA standard for the HP 9000 Series 700 workstations (.pdf) Vicente Cavanna and Christopher S. Liu (December 1992, Hewlett-Packard Journal) pp. 78
LASI
LASI is an highly integrated chipset primarily designed for cost-reduction while still providing most I/O functions. It was used as the main controller in most PA-7100LC and PA-7300LC systems, while later 64-bit PA-8x00 systems used LASI for complementary I/O functions.
The primary cost reductions were achieved by integrating the major I/O subsystems into a single chip. Large parts of the LASI chip are consumed by the LAN and SCSI controller (LAN SCSI), which both being third party designs (NCR and Intel). Other I/O functions are HP-internal standard designs, some taken over from previous HP ASICs and some designed specifically for LASI. The memory and I/O controller was not contained in the chipset but provided by the on-CPU MIOC on the PA-7100LC and PA-7300LC processors or the main chipset controller in the PA-8x00 systems.
Features
- GSC bus interface
- Up to four LASI chips can be used on a single GSC bus (apparently never implemented)
- Intel i82C596CA 10 Mbit Ethernet controller
- NCR 53C710 Fast-Narrow SE SCSI-2 controller
- NS16550A compatible RS232
- WD16C522 compatible
- Harmony CD-quality 16-bit sound
- optional expansion, support for two lines
- up two PS/2 style keyboard and mouse devices
- External 8-bit bus to connect flash EPROMs and a FDD controller (WD37C65C)
- Bus arbitration
- Interrupt controller
- Real-Time clock (RTC)
- PLL generator for the whole I/O subsystem
- 13.2×12.0 mm2 die, 520,000 FETs, 0.8µ (micron), CMOS (HP CMOS26B process), packaged in 240-pin MQUAD
- 3W power consumption at 40 MHz
Used in
- 712, 715, 725, 743i, 745, 744, 748i
- A180, A180C
- B132L, B132L+, B160L, B180L+
- C100, C110, C132L, C160L, C160, C180, C200, C240, C360
- D-Class
- E25, E35, E45, E55
- J200, J210, J210XC, J280, J282, J2240
- K-Class
- RDI PrecisionBook 132, 160, 180
- R380, R390
- SAIC Galaxy 1100
References
- 712 I/O Subsystem
ERS (External Reference Specification) —
LASI ERS
Hewlett-Packard Company (February 1993, Revision 1.1) - An I/O System on a Chip Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)
Stretch
Stretch is the chipset used in a small range of systems, based on 64-bit PA-RISC processors but with Itanium (Merced) main buses. It consists of four main components that are improved previous designs.
- Prelude memory controller is the central part of the system that connects the main memory to two system buses.
- DEW Runway ports/converters convert the system buses into Runway buses for the CPUs — each pair of two CPUs share one DEW. Common configurations include 1-4 DEWs for up to eight processors. Processor types from the PA-8500 upwards are supported.
- IKE I/O controllers attach PCI bridges via I/O links to the system bus. Common configurations are one IKE for each of the two system buses. IKEs then connect to the various PCI bridges.
- Elroy PCI bridges convert the I/O channels from IKE I/O controllers into PCI buses, which provide PCI slots and core functions.
» For illustration view a system-level description of the N4000 server (Stretch-based).
Used in
References
- hp server rp7400 whitepaper, Hewlett-Packard Company (February 2002, product number 5981-0154EN) [did not find an appropriate URL for this PDF document —Ed.]
- rp7400 Hardware Manual (PDF) Hewlett-Packard Company (May 2002)
- hp server rp5400 series entry-level UNIX servers technical whitepaper, Hewlett-Packard Company (August 2002) [did not find an appropriate URL for this PDF document —Ed.]
Cell
The Superdome and various smaller systems from HP used a cell-based system
architecture or Central Electronics Complex
(CEC) which was based on interconnecting
individual system/processor cells via central crossbars. The cell boards were seated in
the backplane of the system, which provided the cell-to-cell links and I/O functionality.
- Cell controller (CC): the central chipset and crossbar of these systems. One sits at
the centre of each cell board for a maximum of two in the complete system. The CCs provide
links for:
- Up to four Processors (8.0 GB/s)
- Up to two Memory
banks
(4.0 GB/s peak) - I/O via SBA (cell to I/O communication is 2.0 GB/s peak)
- PDH (processor dependent hardware) and firmware/flash etc.
- Second cell via XBC (cell-to-cell communication is 8.0 GB/s peak)
- Master I/O controller (SBA): the central I/O part of the main chipset, with one SBA
reserved for each cell/CC, located on the (I/O) backplane.
Each SBA provides sixteen 12-bit links (
ropes
) — the links/ropes from the SBAs connect to slave I/O controllers (LBAs) which in turn connect the PCI I/O slots and I/O subsystems - Core I/O: provides the standard I/O functions for the system. Made up of cards or card sets, which plug into PCI or special slots and provide third-party I/O functions. Distinct cards were availaible/possible: MP/SCSI card and LAN/SCSI, among others. These cards contain a variety of I/O chips, including Ultra160 SCSI, Ultra2-Wide SCSI, Gigabit Ethernet LAN. Ethernet for management LAN, serial ports for management and console, etc.
Other parts of the chipset are made up from already known components:
- Prelude memory controllers (on each cell board) from the Stretch chipset (used in earlier N4000s and L1500/L3000)
- Elroy PCI bridges (LBAs) convert the links/ropes from the SBA into PCI bus
Used in
- N4000 (rp7405, rp7410)
- Superdome
References
- hp server rp7410 whitepaper, Hewlett-Packard Company (March 2002, product number 5980-9997EN) [did not find an appropriate URL for this PDF document —Ed.]
- User Guide hp rp7405/7410 Servers (PDF) Hewlett-Packard Company (2002, third edition)
zx1
The zx1 chipset was designed for HP Itanium-based systems but used in some of the later PA-RISC based servers as well. It consists of two purpose-built main parts that connect the processor, memory and I/O to the Itanium system main buses:
- Pluto zx1 memory and I/O controller (MIO) is the main chipset controller
and connects the three central system buses:
- Processor bus
- Two independent memory buses
- I/O channels (I/O ropes)
- Mercury zx1 I/O adapters (IOAs) connect PCI-X/AGP slots and I/O devices to Pluto
The rest of the I/O chipset is made up of standard third-party I/O parts, such as SCSI controllers, Ethernet devices etc.
Used in
- rp3410, rp3440, rp4410, rp4440, rp7420
- rx1600, rx1620, rx2600, rx2620, rx2660 rx3600, rx5670, rx6600, rx7620, rx7640, rx8620, rx8640
- Superdome
- zx2000, zx6000
Wax
Wax is a secondary I/O controller complimentary to the LASI chipset. It implements various secondary I/O functions and acts as a I/O bus to GSC adapter for different external buses as EISA, HP-HIL and HP-IB. Most systems use it to complement LASI with other required I/O functions that were previously implented in diverse I/O ASICs. It is implemented in the same process and package as LASI.
Features
- GSC bus interface with GSC+ features
- EISA bus converter
- Interfaces GSC to the 32-bit EISA, so EISA devices can attach
- Does not provide complete EISA bus conversion — provides an
Intel i486-like
bus interface, to which external EISA chips attach - Interfaces to external EISA controller: TI TACT84500 (provides EISA bus control unit EBCU and EISA peripheral control unit EPCU
- Integrates the EDPU (EISA data path unit) functionality on-chip
- Attaches to i486 bus for control, bus and IRQ, and directly to EISA for data
- Can be switched at power up to operate as ISA controller (to directly interface with ISA-only devices such as Token Ring controllers etc.)
- Serial interface — NS16550A compatible RS232 (software-compatible with LASI circuitry)
- HP-HIL interface, compatible to previously separate HP HIL chip (1820-4784) used in older workstations
- HPIB interface for instrumentation devices, needs three external chips
- Interrupt control
- Timers (real time, watchdog)
- 0.8µ (micron) CMOS (HP CMOS26B process), packaged in 240-pin MQUAD
- Wax chip numbers: 1FT4-0001
Used in
- 715, 725, 743i, 745, 744, 748i
- B132L, B132L+, B160L, B180L+
- C100, C110, C132L, C160L, C160, C180, C200, C240, C360
- D-Class
- E25, E35, E45, E55
- J200, J210, J210XC, J280, J282, J2240
- R380, R390
References
- External Reference Specification (ERS) for the Wax I/O ASIC Hewlett-Packard Company (May 1993, version 1.0 redacted)
Dino/Cujo
Dino is the GSC to PCI bridge found in many older PCI PA-RISC workstations. The GSC and PCI buses do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions.
Cujo is a Dino bridge with 64-bit PCI.
Features
- GSC bus interface with GSC+ features
- Mapping register with 8 MB resolution
- Integrated PCI arbitration
- Integrated interrupt register
- Supports >40 MHz GSC operation
- Supports >33 MHz PCI operation
- Two PS/2 interfaces
- RS-232 port
- Supports both 3.3 V and 5.0 V PCI operation
- 208-pin PQFP package
- Dino chip numbers: 1FC3-0004
Used in
- A180, A180C
- B132L, B132L+, B160L, B180L+
- C132L, C160L, C160, C180, C200, C240, C360
- J2240
- RDI PrecisionBook 132, 160, 180
References
- DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge Hewlett-Packard Company (February 1997, Revision 3.0)
- Dino 3.1 (1FC3-0004) Errata Listing Hewlett-Packard Company (September 1997)
Elroy
Elroy is a PCI bus bridge that attaches one PCI bus to one or more I/O ropes.
Common configurations are one 250 MB/s I/O rope for one Turbo
PCI bus (can have multiple
slots or attach multiple I/O devices) or two I/O links (about 500 MB/s) for one Twin Turbo bus.
Elroy was often used with the Astro memory and I/O controller.
Features
- Peak bandwidth of up to 500 MB/s
- Attaches to one or more I/O ropes
- Provides one PCI bus
- Multiple Elroys can be used in a single system
- Support for Turbo and Twin Turbo slots — attached via one or two links respectively
- Support for PCI 2.1, 1X, 2X and 4X bus
- PCI data width of 32 or 64 bit
- PCI clock of 33 or 66 MHz
Used in
- A400 (rp2400, rp2430), A500 (rp2450, rp2470)
- B1000, B2000, B2600
- C3000, C3600, C3700
- J5000, J5600, J6000, J6700, J7000, J7600
- L1000 (rp5400), L2000 (rp5450), L1500 (rp5430), L3000 (rp5470)
- N4000 (rp7400), N4000 (rp7405, rp7410),
References
- Elroy ERS (External Reference Specification) — Ropes to PCI Bridge Chip Hewlett-Packard Company (January 2000, Revision A (1.4))
Mercury (zx1)
Mercury is a PCI/AGP bridge for systems based on I/O ropes. It is part of the zx1 chipset used on Itanium systems (called zx1 I/O adapter), and based on the Elroy PCI bridge, extending it for AGP devices and faster I/O ropes. Most systems use several Mercury chips to attach PCI/AGP buses to the multiple I/O ropes. Each Mercury attaches one PCI or AGP bus to up to four 500 MB/s I/O ropes.
Mercury is most often used together with the Pluto I/O and memory controller of the zx1 chipset.
Features
- Attaches to one to four (bundled) I/O ropes
- Provides one PCI, PCI-X or AGP 2.0 bus
- Multiple Mercurys can be used in a single system
- Support for PCI 2.1, also some support for PCI 2.2
- Support for PCI-X
- Support for AGP 1X, 4X and 4X
- PCI data width of 32 or 64 bit
- PCI clock of 33 or 66 MHz
- PCI-X clock of up to 133 MHz
- Up to six PCI slots
- No support for 5 V PCI
Used in
- rp3410, rp3440, rp4410, rp4440, rp7420
- rx1600, rx1620, rx2600, rx2620, rx2660 rx3600, rx5670, rx6600, rx7620, rx7640, rx8620, rx8640
- Superdome
- zx2000, zx6000
References
- HP zx1 ioa ERS External Reference Specification Ropes to AGP/PCI/PCI-X Bridge (.pdf) Hewlett-Packard Company (April 2003, Revision 3.2)
U2/UTurn
U2 and UTurn I/O adapters (IOAs) attach I/O devices and buses (GSC) to the Runway CPU bus on systems with PA-7200, PA-8000 and PA-8200 processors. On the I/O side they provide two GSC (HSC) buses to which other I/O chips and bridges or chipsets attach.
U2 is the variant for PA-7200 systems while all later systems use the UTurn follow-on.
Details
- UTurn/U2 consist of two seperate I/O adapters — IOA A and IOA B
- Runway bus interface to CPU/memory bus, 64-bit wide, 120 MHz, 960 MB/s peak bandwidth
- U2: Two GSC+/HSC I/O buses, peak bandwidth between 128 MB/s to 160 MB/s each
- UTurn: Two GSC-2 I/O buses, peak bandwidth 256 MB/s each (probably, GSC-2 could also be limited to PA-8200 systems)
- Support for various frequencies on both sides (Runway and GSC)
- Address translation from 32-bit GSC to 40-bit Runway addresses
- Hardware cache coherent I/O
- Interface to processor dependent hardware (PDH) on IOA A
- Real-time clock
- U2 is a 432-pin PGA chip, chip numbers: 1MM6-0004
Used in
References
- Visualize J200, J210 technical reference manual (.pdf) p. 23 (2-2) Hewlett-Packard (September 1996)
- Symmetric Multiprocessing Workstations and Servers System-Designed for High Performance and Low Cost (.pdf) William R. Bryg, Kenneth K. Chan, and Nicholas S. Fiduccia (February 1996: Hewlett-Packard Journal)
SIU/SPI
The first PA-RISC processors (1.0) used external support chips to attach the CPU to memory and I/O. This functionality was in later processors integrated into single chips and then moved to the CPU altogether.
The bus setup and structure is similar on NS-1, NS-2 and PCX processors with the SMB CPU attachment but uses different support chips.
NS-1:
- SIU (system interface unit) attaches the CPU to the SMB system main bus (64-bit)
- Two CCUs (cache controller units CCU0 and CCU1) for the cache access
- Physical address space of 29-bit (512 MB main memory could be addressed)
- Memory is attached to the SMB main bus
- I/O is attached to the SMB main bus (with two 32-bit converters on the CTB)
- Cache is attached to the CCUs which attach to the CPU
NS-2:
- SIU (system interface unit) for the system and memory bus
- Two CCUs (cache controller units, split into instruction and data — ICCU and DCCU)
- Physical address space of 29-bit (512 MB main memory could be addressed)
- Memory is attached to the SMB main bus
- I/O is attached to the SMB main bus (with two 32-bit converters on the CTB)
- Cache is attached to the CCUs which attach to the CPU
PCX:
- SPI (SMB to processor interface)
- Three CMUX (cache multiplexer — one instruction, two data)
- Physical address space of 29-bit (512 MB main memory could be addressed)
- Memory is attached to the SMB main bus
- I/O is attached to the SMB main bus (with two 32-bit converters over the CTB)
- Cache is attached to the CMUXs which attach to the CPU
Viper
Viper is the memory and I/O controller (MIOC) on systems with PA-7000 and PA-7100 processors. The chip is similar on both, and sometimes counted into the ASP I/O chipset.
Viper interfaces with PBus to the processor and VSC to the system main bus. It handles all memory and I/O traffic between the processor and the rest of the system.
Bus attachments
- Viper attaches with 32-bit multiplexed address/data bus (PBus) to the CPU
- Memory attaches directly to Viper, with multiplexed 64-bit ECC
- VSC system main bus attaches to Viper (32-bit on PA-7000, 64-bit on PA-7100)
- System main bus interface via two custom ASICs (system bus interface SBI)
- I/O attaches with bus adapters to VSC bus
Details
- Also called Memory and I/O controller (MIOC), Processor Memory Interface (PMI) and Processor Interface Chip (PIC)
- On SMP systems two connections strategies supported: Each CPU has its own MIOC which share a SMB bus and memory, or two CPUs share one MIOC
- 9,5×9,5 mm2 die, 185,000 FETs, 0.8µ (micron), CMOS (CMOS26B) in 272-pin CPGA
- Newer/different Viper design: 0.8µ (micron), CMOS (CMOS26B) in 408-pin PGA
- SBI system bus interface: two 100-pin QFP chips
- Low-cost version on the 705/710 workstations: two separate chips, each 7,0×7,0 mm2 die, 1.0µ (micron), two-layer metal CMOS (CMOS34) in 160-pin QFP
- Viper (PA-7000) chip numbers: 1FV8-0002
Used in
- 705, 710, 715, 725, 720, 730, 750, 735, 755, 742i, 745i, 747i
- Nova servers (F, G, H, I-Class)
- 890, T500, T520
- Mitsubishi ME/R7200, ME/S7200, ME/R7300, ME/S7300, ME/R7500, ME/S7500
- Hitachi 3050RX 220, 230, 310S, 320, 330, 430, 440, 9000V V735/125, VT500
References
- Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
- VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)
- High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) pp. 56-63 Craig Fink et al (August 1992: Hewlett-Packard Journal)
Memory and I/O Controller (MIOC)
The Memory and I/O Controller in the PA-7100LC and PA-7300LC processor integrates DRAM/cache and I/O controller onto the processor die. It is similar on both CPUs, with the PA-7300LC MIOC having wider data paths to L2 cache and RAM and supporting the advanced GSC+ bus over the older GSC.
The integrated memory controller requires only buffers and DRAM modules to build up the complete memory subsystem. The PA-7300LC memory controller includes a Second Level Cache Controller (SLC), which provides an optional L2 cache, ranging from 32 KB to 8 MB. It shares the data bus with the DRAM subsystem, so it has the same width (64/128-bit) and same optional SEDC error control.
Details
- Execution units and internal caches attach on-chip to the MIOC
- External cache (L1 on PA-7100LC, L2 on PA-7300LC) attach to MIOC via 64-bit (PA-7100LC) or 128-bit (PA-7300LC), both with ECC
- Memory attaches to MIOC via 64-bit (on PA-7100LC) or 128-bit (PA-7300LC), with ECC
- On PA-7300LC memory lines use the L2 cache data lines
- GSC, the system main bus attaches to MIOC
- On PA-7300, GSC+ system main bus
- Support for 4, 16, 64 and 256 Mbit modules
- Support for both FPM and EDO DRAM
- Optional SEDC error control
- Up to 16 physical memory slots
- Support for a wide range of core frequencies
- Support for 3.3 V and 5.0 V DRAM
Used in
- 712, 715, 725, 743i, 745, 744, 748i
- A180, A180C
- B132L, B132L+, B160L, B180L+
- C100, C110, C132L, C160L, C160, C180, C200, C240, C360
- D-Class
- E25, E35, E45, E55
- J200, J210, J210XC, J280, J282, J2240
- K-Class
- RDI PrecisionBook
- R380, R390
- SAIC Galaxy 1100
- Hitachi 3050RX 225, 235, 255, 535, e9000V V715, V715Tiny, VE25, VE35, VE45, VE55
References
- PA7100LC ERS (External Reference Specification) (.pdf) Hewlett-Packard Company (1999)
- The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment Mick Bass et al (April 1995: Hewlett-Packard Journal. Accessed May 2009)
- PA7300LC ERS (External Reference Specification) (PDF, 716 KB) Hewlett-Packard Company (1996)
-
The PA-7300LC: the first
System on a Chip
(archive.org mirror) Tom Meyer (1996: Presentation for Microprocessor Forum 1995)
DEW (Stretch)
DEW is the Runway CPU bridge for systems based on the Stretch chipset. It attaches the Runway-based PA-8500, PA-8600 and PA-8700 CPUs to the Itanum-based system man buses. Each pair of two CPUs share one DEW port converter. Common configurations include one to four DEWs for up to eight processors.
Details
- CPU side: Runway+/Runway DDR processor bus for up to two PA-8x00 processors with peak bandwidth of 2.1 GB/s
- System side: Itanium system bus at 133 MHz, with 2.1 GB/s peak
- Up to four DEWs were implemented in actual single systems for up to eight processors
Used in
References
- See Stretch chipset references
MMC/SMC
Most systems with a PA-7200, PA-8000 or PA-8200 processor use a combination of the MMC and SMC memory controllers to attach the main system memory to the Runway processor bus. The I/O is controlled by the U2/UTurn I/O adapters on the same Runway bus.
Details
- Master Memory Controller (MMC) is the main memory controller and attaches with 64-bit to the Runway processor bus and 128-bit to the memory data bus (via the DMs)
- Slave Memory Controllers (SMCs) are the secondary memory controllers and attach to the MMC main memory controllers. Up to eight SMCs attach to one MMC on its memory address bus. The SMCs carry the functionality to interface with specific types of DRAM.
- Data Multiplexers (DMs) attach the 128-bit 60 MHz data bus of the MMC to the four sets of memory. Each two sets of memory connect with two 64-bit 30 MHz buses to the DMs. The DMs are not used in all systems.
- Memory data bus from MMC to DMs/memory 128-bit wide, with 60 MHz peak bandwidth (960 MB/s data rate)
- Physical address space of 36-bit (32 GB main memory)
- Memory address bus is shared between all SMCs of a MMC, 39-bit at 60 MHz
- Memory data bus attaches to the DMs and memory
- Memory attaches to their private SMCs for addresses and to Data MUXes for data
- Up to 32-way memory interleaving (four-way per SMC)
- MMC is a 432-pin PGA chip
- SMCs are 208-pin MQUAD chips
- DMs are 160-pin POFP chips
Used in
References
- A New Memory System Design for Commercial and Technical Computing Products (.pdf) Thomas R. Hotchkiss, Norman D. Marschke, and Richard M. McClosky (Februar 1996: Hewlett-Packard Journal)
- And cf. the references of U2/UTurn above
Prelude (Stretch)
Prelude is the memory controller of systems with the Stretch chipset and connects the main memory via four memory buses to two system buses. The main buses are in fact Itanium/Merced buses in preparation of the HP shift from PA-RISC to Itanium. Systems with Stretch theoretically could have been upgraded to Itanium processors, which however never realized.
Details
- Two system buses, each 2.1 GB/s peak with 4.3 GB/s aggregate
- Up to four memory buses, each 2.1 GB/s peak with 8.6 GB/s aggregate to the memory
- Both memory and system buses are Itanium/Merced buses at 133 MHz DDR with 64-bit width, ECC-protected
- System main buses connect to the CPU bridges (DEW) and I/O controllers (IKE)
- SDRAM memory
- Up to 16 pairs of DIMMs supported
- Prelude consists of three VLSI chips: one address controller and two data controllers; each data controller drives two multiplexed 64-bit memory buses
Used in
References
- See Stretch chipset references
Astro
Newer workstations and servers, based on PA-8500, PA8600 and 8700 processors, use the Astro chip for memory and I/O management (IOMMU). Pluto is the successor of Astro for Itanium-2 processors and buses; it works very similar.
Astro attaches to three different buses and is the central part of the chipset:
- Processor system bus — Runway+/Runway DDR for up to two PA-8x00 processors with a maximum lock of 125 MHz and peak bandwidth of about 2.0 GB/s with DDR
- Memory bus with a peak bandwidth of 2.0 GB/s at maximum clock of 125 MHz (the memory bus is a variant of Runway)
- I/O system buses made up from up to eight single I/O links (ropes) which attach to individual PCI bridges (mostly Elroy chips) which convert each one or two I/O links into a PCI bus. Peak aggregate I/O bandwidth is 2.0 GB/s
Features
- Support for 120/125 MHz SDRAMs
- Maximum supported memory of 40 GB
- PCI 2.1 compliant
- 16-entry fully associative I/O TLB
- 16-entry fully associative coherent I/O buffer cache
- Up to eight I/O links (ropes) — each 10-bit, 133 MHz with datarate of 250 MB/s; aggregate maximum 2.0 GB/s
- 664-pin ceramic LGA
- Generates about 20W
- Astro chip numbers: 1QM2-0004, 1ST8-0002
Used in
- A400 (rp2400, rp2430), A500 (rp2450, rp2470)
- B1000, B2000, B2600
- C3000, C3600, C3700
- J5000, J5600, J6000, J6700, J7000, J7600
- L1000 (rp5400), L2000 (rp5450)
References
- Astro
External Reference Specification Introduction
Astro External Reference Specification Error Handling
Astro External Reference Specification R2I Operations
Astro External Reference Specification Register Map
Astro External Reference Specification Runway Interface
Astro External Reference Specification Memory Map
Hewlett-Packard Company (February 2000, Revision 1.2)
Pluto (zx1)
Many of the Itanium-based HP workstations and servers use the Pluto I/O and memory controller as part of the zx1 chipset. Pluto is based on the Astro IOMMU, extending it for Itanium-2 processors and bus interfaces, DDR memory and faster I/O links.
Pluto is a IOMMU and attaches to three different buses, acting as central crossbar:
- Processor bus: Itanium-2 processor bus for one to four CPUs. The bus runs at maximum of 200 MHz with a width of 128-bits and has ECC-protection, for up to 6.4 GB/s data rate.
- Two memory bus with a peak bandwidth of aggregated 8.0 GB/s at maximum clock of 266 MHz DDR. Can be extended with the zx1 SME for more memory and higher peak datarate of 12.8 GB/s
- I/O system based on eight separate 500 MB/s I/O links (ropes) which attach to individual PCI, PCI-X or AGP bridges. Peak aggregate I/O bandwidth is 3.2 GB/s
Features
- Support for DDR SDRAMs
- Maximum supported memory of 16 GB (with 256 Mb DRAMs) or up to 64 GB with SME memory extender
- Integrated I/O cache controller (IOCC)
- 16-entry I/O TLB
- 16-entry coherent I/O cache
- IOCC can serve as AGP GART
- Two rope quad controllers (RQCCs) that each control up to four I/O ropes and attach to the IOCC
- Each RQCC can bundle the four I/O ropes into single, double or quad-wide bundles.
- Up to eight I/O ropes with a clock of up to 266 MHz (500 MB/s peak data rate), aggregate peak would be 4,000 MB/s (which Pluto cannot sustain)
- 664-pin ceramic LGA
- Generates about 20W
- Astro chip numbers: 1QM2-0004, 1ST8-0002
Used in
- rp3410, rp3440, rp4410, rp4440
- rx1600, rx1620, rx2600, rx2620, rx2660 rx3600, rx5670, rx6600, rx7620, rx7640, rx8620, rx8640
- Superdome
- zx2000, zx6000
References
- zx1 mio (Memory and I/O) External Reference Specification Hewlett-Packard Company (March 2003, Revision 1.0)
IKE (Stretch)
IKE is the I/O controller on systems with the Stretch chipset.
The central memory controller provides one or two system buses, to which CPUs and
I/O attach.
Each system bus has one IKE I/O controller that connects to several slave I/O
controllers (Elroy PCI bridges), which in turn provide PCI buses.
The connection between IKE and each slave I/O controller is one or two
12-byte wide I/O links (I/O ropes).
I/O channels can be combined into twin I/O channels for so-called Twin-Turbo
PCI slots/buses.
Details
- System side connects to system main bus, a Itanium bus at 133 MHz, with 2.1 GB/s peak
- I/O side attaches to up to twelve 12-byte wide 266 MB/s I/O links
- Each PCI slot has its own PCI controller and bus
- Elroy PCI bridges convert the I/O channels into PCI buses
Used in
References
- See Stretch chipset references