PA-RISC Chipsets
ASP
Used in
- 705 and 710
- 715
- 725
- 720, 730, 750
- 735 and 755 (ASP2)
- 742i
- 745i
- 747i
ASP is the the chipset used in all older PA-RISC workstations, still being
a classical
chipset, it includes several different chips to provide the
I/O subsystem. It includes several modules from 3rd party vendors to complete the system.
The ASP2 chipset, used in the 735 and 755 workstations, offers some small
feature improvements (faster SCSI and addditional FDDI networking).
Features
- Viper memory controller
- NCR 53C700 8-bit Narrow single-ended SCSI-2
- ASP2: NCR 53C720 16-bit Fast-Wide differential SCSI-2
- Intel 82596DX 10Mb Ethernet controller
- Intel 82501AD Ethernet transceiver, media auto-selection
- ASP2: AMD Formac Plus Am79C830 FDDI controller (ASP2)
- ASP2: Stereo/CD quality audio
- WD 16C552 parallel
- NS 16550A compatible serial
- 512KB EPROM — the Boot ROM
- 8KB EEPROM for storing system configuration status etc.
- Intel 8042 microprocessor controlling:
- Battery backed RTC
- System & user timers
- Audio generator
- HP-HIL interface
- Frontpanel system status LEDs
References
- Hardball I/O Subsystem, External Reference Specification
- Hewlett-Packard Company (September 1991, Version 1.1).
Astro
Used in
- A400 (rp2400, rp2430), A500 (rp2450, rp2470)
- B1000, B2000, B2600
- C3000, C3600, C3700
- J5000, J5600, J6000, J6700, J7000, J7600
- L1000 (rp5400), L2000 (rp5450)
Newer workstations and servers use the Astro chip for memory and I/O management. It includes most of the functions on a single die, requiring only few additional peripheral ASICs to interface and drive the specific buses.
Astro attaches to three different buses and is the central part of the chipset:
- Processor system bus — Runway for (theoretically) up to two PA-8x000 processors with a max. clock of 120MHz and max. bandwidth of 1.9GB/s
- Memory bus with a max. bandwidth of 1.9GB/s
- I/O system buses made up from up to eight single I/O links (ropes) which attach to individual PCI bridges — in most cases Elroy chips which convert each one or two I/O links into a PCI bus
There are several different variants of Astro.
Features
- System/processor bus bandwidth of 1.9GB/s
- Memory bandwidth of 1.9GB/s
- Up to eight I/O links (ropes) — each 250MB/s, aggregate maximum 2.0GB/s
- Support for 125MHz SDRAMs
- Maximum supported memory of 40GB
- PCI 2.1 compliant
- 16-entry fully associative I/O TLB
- 16-entry fully associative coherent I/O buffer cache
References
- Astro
External Reference Specification Introduction
Astro External Reference Specification Error Handling
Astro External Reference Specification R2I Operations
Astro External Reference Specification Register Map
Astro External Reference Specification Runway Interface
Astro External Reference Specification Memory Map - Hewlett-Packard Company (February 2000, Revision 1.2).
Dino/Cujo
1FC3-0004
Used in
- A180, A180C
- B132L, B132L+, B160L, B180L+
- C132L, C160L, C160, C180, C200, C240, C360
- J2240
- RDI PrecisionBook 132, 160, 180
Dino is the GSC-to-PCI bridge found in most older PCI-based PA-RISC workstations. The GSC and PCI bus do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions.
Cujo is a Dino bridge with a 64-bit datapath.
Features
- Implements GSC+ features
- Mapping register with 8MB resolution
- Integrated PCI arbitration
- Integrated interrupt register
- Supports >40MHz GSC operation
- Supports >33MHz PCI operation
- Two PS/2 interfaces
- RS-232 port
- Supports both 3.3V and 5.0V PCI operation
- 208-pin PQFP package
References
- DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge
- Hewlett-Packard Company (February 1997, Revision 3.0).
- Dino 3.1 (1FC3-0004) Errata Listing
- Hewlett-Packard Company (September 1997).
Elroy
Used in
- A400 (rp2400, rp2430), A500 (rp2450, rp2470)
- B1000, B2000, B2600
- C3000, C3600, C3700
- J5000, J5600, J6000, J6700, J7000, J7600
- L1000 (rp5400), L2000 (rp5450)
- L1500 (rp5430), L3000 (rp5470)
- N4000 (rp7400)
- N4000 (rp7405, rp7410)
- rp3410, rp3440
- rp4410, rp4440
- rp7420
- Superdome
Elroy is the chip used to attach a PCI bus to the system and I/O buses in the various newer PA-RISC systems.
Each Elroy chip attaches one PCI bus to one or more of the I/O system’s I/O channels — ropes.
Common configurations are one I/O link (about 250MB/s) for one Turbo
PCI bus (can have multiple
slots or attach multiple I/O devices) or two I/O links (about 500MB/s) for one Twin Turbo bus.
Elroy is also called LBA one some of the newer systems.
Features
- Peak bandwidth of up to 500MB/s
- Attaches to one or more I/O links — ropes
- Provides one PCI bus
- Multiple Elroys can be used in a single system
- Support for Turbo and Twin Turbo slots — attached via one or two links respectively
- Support for PCI 2.1, 1X, 2X and 4X protocol
- PCI data width of either 32 or 64 bit
- PCI clock of 33 or 66MHz
References
- Elroy ERS (External Reference Specification) — Ropes to PCI Bridge Chip
- Hewlett-Packard Company (January 2000, Revision A (1.4)).
LASI
1FT1-0002, 1FU2-0002
Used in
- 712
- 715
- 725
- 743i
- 744
- 748i
- A180, A180C
- B132L, B132L+, B160L, B180L+
- C100, C110, C132L, C160L, C160, C180, C200, C240, C360
- D-Class
- E25, E35, E45, E55
- J200, J210, J210XC, J280, J282. J2240
- K-Class
- RDI PrecisionBook 132, 160, 180
- R380, R390
- SAIC Galaxy 1100
Designed for and firstly used in the 712 series workstations the LASI I/O chip was similarly designed for cost-reduction. One of the major objectives of the 712 I/O subsystem was to provide similar or equal functionality and performance like other 700 series systems (e.g. 720, 730, 715 Scorpio) at a significantly reduced manufacturing cost. The design team finally concluded that integrating major parts of the I/O subsystem into one large VLSI chip would reduce the fabrication cost significantly, as required. The majority of circuitry in LASI is consumed by the two most important parts: LAN and SCSI (therefore LAN SCSI). Both of these designs were purchased from third party companies (NCR and Intel) and integrated as so-called mega-cells in the VLSI chip. The other I/O functions originate from HP internal standard cell designs, some of whom were leveraged from previous HP ASIC designs and some designed specifically for LASI.
Features
- LAN — Intel i82C596CA 10Mb Ethernet controller
- SCSI — NCR 53C710 Fast-Narrow SE SCSI-2 controller
- Serial — NS16550A compatible RS232
- Parallel — WD16C522 compatible
- Audio — Harmony CD-quality 16-bit sound
- Telephony — optional expansion, support for two lines
- Human Interface — support for two PS/2 style keyboard and mouse devices
- FDD and boot ROM — external 8-bit bus to connect flash EPROMs and a FDD controller (WD37C65C)
- Interface to GSC bus
- Bus arbitration
- Interrupt controller
- Real-Time clock (RTC)
- PLL generator for the whole I/O subsystem
Besides this chip only very few parts are needed to build a
complete system: CPU, cache, RAM and a graphics adaptor. It is furthermore
possible to use up to four LASI chip on a single GSC bus.
The LASI chip was designed in a 0.8u CMOS process and is 13.2 x 12.0 mm2
in size. It contains 520,000 FETs and is packaged in a 240-pin MQUAD
package. It consumes about 3W when operating an 40MHz.
References
- 712 I/O Subsystem
ERS (External Reference Specification) —
LASI ERS
- Hewlett-Packard Company (February 1993, Revision 1.1).
- An I/O System on a Chip
- Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal).
Cell-based (Superdome)
Used in
- N4000 (rp7405, rp7410)
- Superdome
The Superdome and various smaller systems from HP used a cell-based system
architecture or Central Electronics Complex
(CEC) which was based on interconnecting
individual system/processor cells via central crossbars. The cell boards were seated in
the backplane of the system, which provided the cell-to-cell links and I/O functionality.
- Cell controller (CC): the central chipset and crossbar of these systems. One sits at
the centre of each cell board for a maximum of two in the complete system. The CCs provide
links for:
- Up to four Processors (8.0GB/s)
- Up to two Memory
banks
(4.0GB/s peak) - I/O via SBA (cell to I/O communication is 2.0GB/s peak)
- PDH (processor dependent hardware) and firmware/flash etc.
- Second cell via XBC (cell-to-cell communication is 8.0GB/s peak)
- Master I/O controller (SBA): the central I/O part of the main chipset, normally one SBA
is reserver for each one cell/CC but located on the (I/O) backplane.
Each SBA provides sixteen 12-bit links (
ropes
) — the links/ropes from the SBAs connect to slave I/O controllers (LBAs) which in turn connect the PCI I/O slots and I/O subsystems - Core I/O: provides the standard I/O functions for the system. Made up of cards or card sets, which plug into PCI or special slots and provide third-party I/O functions. Distinct cards were availaible/possible: MP/SCSI card and LAN/SCSI, among others. These cards contain a variety of I/O chips, including Ultra160 SCSI, Ultra2-Wide SCSI, Gigabit Ethernet LAN. Ethernet for management LAN, serial ports for management and console, etc.
Other parts of the chipset are made up from already known components:
- Prelude SMC memory controllers (on each cell board) from the Stretch chipset (used in earlier N4000s and L1500/L3000)
- Elroy PCI bridges (LBAs) convert the links/ropes from the SBA into PCI bus
References
- hp server rp7410 whitepaper, Hewlett-Packard Company (March 2002, product number 5980-9997EN) [did not find an appropriate URL for this PDF document —Ed.]
- User Guide hp rp7405/7410 Servers (PDF) Hewlett-Packard Company (2002, third edition)
Stretch
Used in
Stretch is the chipset or Central Electronics Complex
(CEC) used in a very small range of
systems.
It basically consists of four main components, which build the backbone of the (Runway-based
PA-8x00) processor/memory and I/O system — one central memory controller which connects
all system buses together; Runway ports for attachment of processors to the system bus; I/O
controllers which attach the I/O subsystem to the system bus; PCI bridges, which convert the
I/O subsystem’s links into PCI buses:
- Prelude SMC memory controller is the central part of the system, it connects
the main memory to two system buses (one on each side), to which each one IKE I/O
controller and one or more DEW Runway ports (for each two CPUs) attach (Prelude
is also called
Very Low Latency Memory Controller
) - DEW Runway ports/converters convert the Prelude’s system bus(es) (which in fact is an Itanium/Merced bus) into Runway buses for the various CPUs — each two CPUs share one DEW port converter (CPUs from the PA-8500 upwards supported). Common configurations include 1-4 DEWs for up to eight processors.
- IKE I/O controllers attach each to the system bus. Common configurations are one IKE for each of the two system buses (one on each side). IKEs then connect to the varios PCI bridges.
- Elroy PCI bridges (LBAs) which convert the I/O channels from the IKE I/O controllers into PCI buses, to which the PCI slots and core I/O functions attach. Up to 14 Elroys were used in actual systems.
Features
- Two system buses 133MHz, each 2.1GB/s peak — aggregate 4.3GB/s (these system buses are in fact Itanium/Merced system buses)
- Up to four memory buses, each 2.1GB/s peak — aggregate 8.6GB/s bandwidth to the memory (on the rp7400)
- DEW port converter needed for attachment of PA-8x00 processors to the Merced system bus — up to four DEWs were found in actual systems
- I/O controllers attach to the system bus
- Multiple I/O channel configurations from the IKE I/O controller(s) supported — each 133MHz 256MB/s with eight, twelve or 22 links found in actual systems (2.1GB/s, 3.2GB/s or 6.4GB/s aggregate max bandwidth)
References
- hp server rp7400 whitepaper, Hewlett-Packard Company (February 2002, product number 5981-0154EN) [did not find an appropriate URL for this PDF document —Ed.]
- rp7400 Hardware Manual (PDF) Hewlett-Packard Company (May 2002)
- hp server rp5400 series entry-level UNIX servers technical whitepaper, Hewlett-Packard Company (August 2002) [did not find an appropriate URL for this PDF document —Ed.]