The computers covered by this site are based on PA-RISC processors, implementing the PA-RISC architecture, connected by various buses to the system chipsets, with I/O handled by SCSI controllers and video adapters.
The following systems design and components were used between the 1980s and mid-2000s.
- Early 32-bit systems (1980s TS-1, NS-1, NS-2 and PCX) use custom designs, with most based on the SIU/SPI main bus interfaces attaching the CPU to the SMB bus. In most cases the system processing and I/O units are made up of a large number of individual chips forming the central chipset and using the CIO and HP-PB I/O buses. (Early system designs)
Early 1990s (1991-1994)
- The 32-bit PA-7000 and PA-7100 systems use the ASP chipset and Viper memory controller. They utilize the VSC CPU/memory, GSC system main and SGC and EISA expansion buses, with servers using HP-PB I/O buses, all provided by separate I/O adapters/bus bridges. (ASP/Viper-based system designs)
- PA-7100LC and PA-7300LC systems use the highly integrated LASI chipset, which combines most functions and I/O on a single chip, and an on-CPU MIOC memory controller. These system use GSC or GSC+ as main bus and a variety of expansion buses via bus adapters, ranging from HSC/GSC, EISA to PCI and VME. EISA is provided by Wax, PCI by Dino. (LASI system designs)
- PA-7200 and 64-bit PA-8000 and some PA-8200 systems use the U2/Uturn I/O adapters, which attach two GSC/HSC buses to the main Runway bus, and MMC/SMC memory controllers. I/O is realized on the GSC bus with the LASI chipset and Wax and Dino I/O adapters. (U2/Uturn system designs)
Late 1990s to early 2000s (1998-2002)
- Some PA-8500, PA8600
and PA-8700 systems use a
rope-based architecture with Astro as main system controller and separate Runway+/Runway DDR buses with I/O devices controlled by Elroy PCI bridges. (Astro-based system designs)
- Other 64-bit midrange servers based on the same processors (PA-8500 to 8700) are based on the Stretch chipset, a rather complicated setup with central system controller and links to separate processor and I/O controllers and PCI bridges. Main system bus is the Itanium bus, with converters for the processors’ Runway+/Runway DDR buses. (Stretch system designs)
- The Superdome
mainframeand a smaller server, based on PA-8700 and PA-8800/PA-8900 are based on the Cell chipset, similar to the Stretch, but more scalable. Systems are made up of
cells, with their own central system/memory controller, I/O controller and PCI bridges. (Cell-based architecture)
- The last PA-RISC systems (PA-8800/PA-8900) and several second-generation Itanium systems use the HP zx1 chipset, conceptually similar to Astro systems but with higher datarates and options, based on Itanium 2/McKinley buses. (zx1, Itanium-like system designs)
- Systems from the Exemplar family as the Convex SPP and HP V-Class are based on the Convex Exemplar crossbar architecture.
Several pages on PA-RISC hardware are kept on this site for archival reasons on old content and documentation. They are listed on Archived PA-RISC pages.