OpenPA.net

Chipset section extended (Stretch, zx1, others)

Paul Weissmann

Entries on the Stretch chipset have been improved with more details and sections added for the Itanium/PA-RISC zx1 chipset and its various components.

All other chipset sections have been revised, extended and reordered, with an overview table providing a summary of the chipsets and support chips used in PA-RISC computers.

HP 9000/T600, T520, T500 and 890

Paul Weissmann

The T-Class servers are large 32-bit PA-RISC mainframes from the mid-1990s, built with modular system cards that contain processors, memory or I/O devices.

The HP 9000/890 was an early iteration of the architecture, with the later T500/T600 being updated sucessors. After the 64-bit T600 the basic system design of the T-Class was discontinued in favor of the more flexible SuperDome systems.

Ten years OpenPA.net

Paul Weissmann

December 2009 marks the 10th anniversary of OpenPA.net.

This site started in December 1999 (under a different title and URL) at a time when Google just started operating and Wikipedia didn't exist yet. It has been a long and rewarding time maintaining this resource on PA-RISC computing.

About 1.7 million visitors accessed this site since December 1999, according to a very rough estimate. Contributions and mails peaked in the early years between 1999-2002, probably owing to the fact that really no other information on PA-RISC was available then, which changed since.

This site was hosted at various locations on sometimes quite bizarre platforms, including a DECstation 5000/200 (25MHz R3000 MIPS!), Alphastations (200 and 255), a HP 9000 712/100, and at some point even on a Motorola MVME187 system.

Thanks to all those who helped making this site happen, with providing infrastructure, services and contributing and correcting content!

CPU buses and attachments

Paul Weissmann

HP used various CPU bus designs to attach the main processor to the main system bus with its I/O adapters and the memory. About five main connection strategies and buses were used, which were added as CPU attachment subsections to new or updated bus entries.

SMB bus attachment on early 32-bit PA-RISC 1.0 CPUs from the 1980s
PBus on 32-bit PA-RISC 1.1 PA-7000 and PA-7100
Direct attachments to the GSC bus on the low-cost PA-RISC 1.1 LC processors have
Runway bus attachments on PA-7200 and 64-bit PA-8000/PA-8200 processors
Runway+/Runway DDR , an advanced Runway variant, on PA-8500, PA-8600 and PA-8700
The last PA-RISC processors, the dual-core PA-8800 and PA-8900 use Itanium 2 processor buses

The PA-RISC processors sections have been updated with the bus information as well.

Memory and I/O controllers

Paul Weissmann

Several forms of memory and I/O controllers (MIOCs) were employed on HP PA-RISC systems. The chipsets page has several updated and new sections:

In early days (NS-1, NS-2 and PCX processors) a combination of support chips for the CPU was used — the SIU/SPI controllers being the main memory and bus controllers
Later on, these chips were integrated into Viper, a single memory controller (PA-7000/PA-7100)
On the LC processors the controller moved as integrated MIOC onto the CPU die (PA-7100LC/PA-7300LC)
Newer Runway-based CPUs (PA-7200, PA-8000/PA-8200) split the MIOC again in different external chips, the U2/UTurn I/O controllers and MMC/SMC memory controllers
Later 64-bit processors (PA-8500, PA-8600 and PA-8700) use a newer Runway+/Runway DDR variant and several I/O and memory controllers, such as Astro, Stretch or Cell
The newest 64-bit processors (PA-8800, PA-8900 and Itaniums) use Itanium chipsets, including the HP zx1

Removal of outdated pages

Paul Weissmann

Several outdated and incomplete pages have been removed from OpenPA. This includes the listings for PA-RISC expansion cards, memory modules and explanations of the PDC Boot ROM and various LED error codes. As these pages had not been updated for many years, their content became less useful, and relevant only for older 32-bit systems. There are other sources with current and complete information on these topics (HP ITRC, HCLs, third-party part number listings, discussion boards). After consideration these pages were removed, as the utility of keeping known outdated pages is doubtful — even more so, if there are better resources elsewhere.

Mainframes: Convex SPP1000, SPP1200 and SPP1600

Paul Weissmann

The Convex Exemplar SPP1x00, introduced between 1994-1996, are scalable 32-bit mainframes, with either PA-7100 (SPP1000) or PA-7200 (SPP1200 and SPP1600) processors. They consist of three distinct system building concepts: the CD compact systems with up to 16 CPUs, the XA eXtended Architecture hypernodes with up to eight CPUs and the XA clusters, consisting of up to 16 linked XA hypernodes, with up to 128 CPUs.

HP started a collaboration with Convex in the mainframe sphere in the early 1990s with these PA-RISC based systems; Convex was later completely bought by HP (in the mid-1990s) and the SPP Exemplar computers integrated into HP’s own HP 9000 portfolio (first the joint-marketed S-Class and X-Class, later the HP V-Class).

The SPP 1x00 mainframes laid the foundation of the Exemplar crossbar architecture, with the 32-bit systems all using the same system design as the original SPP1000. The crossbar design was revised and improved in the 64-bit SPP2000 and later taken over into HP’s own V-Class system, basically only slighly faster SPP2000 systems. The first implementations of the Exemplar crossbar used rare Gallium arsenide gate arrays (GaAs) chips.

Mainframes: HP/Convex SPP2000 (S-Class/X-Class)

Paul Weissmann

The jointly marketed Exemplar SPP2000 (Convex)/S-Class and X-Class (HP) are the 64-bit Exemplar successors to the 32-bit based SPP1x00s from the mid-1990s. The SPP2000 are the direct predecessors of the HP 9000 V-Class systems. They feature a slightly modified SPP1x00 crossbar architecture, upgraded with 64-bit PA-8x00 processors and different clustering attachments. Single nodes can carry more processors (16), more RAM (32GB) and have a different I/O system (PCI) than their predecessors; the clustering ability has been increased twofold — SPP2000 clusters (called “X-Class” by HP) can be built from up to 32 interconnected SPP2000 nodes (“S-Classes” at HP).

In contrast to the SPP1x00 line of Exemplars, the compact CD models — two closely coupled nodes and no SCI clustering attachments — were dropped with the SPP2000 and only the concept of a single node and multiple nodes as cluster retained. Also changed was the SCI (“CTI”) clustering topology — in contrast to the four unidirectional rings (2.4GB/s overall) of the SPP1x00s, clustered SPP2000s form a torus with each of a single node’s eight memory controllers attaching to two SCI rings.

HP X-Terminals page contributed to Wikipedia

Paul Weissmann

The page on HP X-Terminals was contributed (i. e. donated) to Wikipedia as of September 5, 2008. The original content of this site can be freely distributed by Wikipedia. Somehow the X-Terminals page never really belonged to OpenPA — although the stations were often distributed along PA-RISC systems they were more or less just “peripherals” and not really in the focus of this site. Since the page was rarely updated a decision was made to contribute the whole content to Wikipedia, with the hope that it might be useful there. The page will be kept with a boilerplate/reference to Wikipedia for a while, however it is disconnected from the main site and will be removed in the next months.