PA-RISC is Hewlett Packard’s RISC (Reduced Instruction Set Computing) architecture and an 1980s offspring from previous designs such as the FOCUS CPU. The aim was to replace 16-bit stack-based CPUs in HP 3000 servers and Motorola 680x0 CPUs in HP’s Unix systems, with a common system architecture.
Overall PA-RISC was a rather conservative RISC design:
- The instruction set is implemented in hardware and not microcoded.
- Instruction size is of fixed length — one word (32-bit).
- Only three addressing modes: long/short displacement and indexed.
- Only load/store operation access the memory, no computational instructions directly access it.
- Many simple and frequently used instructions execute in just one cycle, more complex computation are assigned to assist processors or software algorithms.
Compared to other RISC architectures from the time the original PA-RISC design was rather unspectacular — it had typically fewer features but remained always at competitive speeds, especially in Floating Point and SMP (multiprocessing) areas. HP was the first to include multimedia extension in commercially available microprocessors (MAX-1 in the PA-7100LC and MAX-2 64-bit in the PA-8000) which allowed vector operations on two or four 16-bit subwords in 32-bit or 64-bit integer registers.
The original PA-RISC 1.0 architecture included a single instruction/data bus; PA-RISC later on moved to a Harvard-style architecture with seperate instruction and data buses. It has thirty-two 32-bit integer general purpose registers (GR0-GR31), seven shadow registers (SR0-SR6) for fast-interrupts and thirty-two 64-bit Floating Point registers for the FPU, which also could be combined to 64×32-bit and 16×128-bit. The FPU is able to execute a Floating Point instruction simultaneously to the ALU. The original addressing was 48-bit wide, it was later on expanded to 64-bit (with the introduction of the PA-8000 line).1
The PA-RISC architecture was extended to version 1.1 with the PA-7000 processor in 1991. The major change in PA-RISC 1.1 was the inclusion of a MMU (memory management unit), that enables the PA-RISC platform to use virtual memory. From the the second PA-RISC 1.1 processor, the PA-7100, onward all processors implement superscalar instruction execution — the ability to execute multiple instructions simultaneously. The 32-bit variants are up to two-way superscalar, later 64-bit processors up to four-way. Other significant developments include the PA-7100LC and PA-7300LC (LC for low cost) processors, which integrate the memory and I/O controller onto the processor die (on the PA-7300LC additionally the cache controller and first-level cache).
In 1996 the 64-bit redesign of the PA-RISC architecture was introduced with the PA-RISC 2.0 PA-8000 processor. The architectural changes were rather intrusive, while staying compatible with the 32-bit PA-RISC 1.1. (On a side note, the PA-8000 was introduced before the last 32-bit processor — the PA-7300LC — shipped.) Main changes in PA-RISC 2.0 include:
- All registers and functional units have been extended to 64-bit
- Virtual address space is 64-bit
- Physical address space is 40-bit on PA-8000 to PA-8600 (1TB of addressable physical memory) and 44-bit (16TB memory) on PA-8700 and later
- Out-of-Order (OoO) execution capability with the IRB (Instruction Reorder Buffer), which stores up to 28 computation and 28 load/store instructions and reorders and prepares the for execution on the fly. It tracks interdependecies and branch prediction outcomes as well. The IRB is the key part in the OoO execution capability of PA-RISC 2.0.
- FPMAC (Floating Point Multiply Accumulate) units
The later PA-8x00 processors did not introduce other significant changes besides higher integration, such as large L1 caches in the PA-8600 and the dual-core PA-8800 and PA-8900. In fact all processors after the PA-8000 were only redesigns and extensions of that processor core.
From the mid-1990s on a parallel track to PA-RISC 2.0 development HP joined Intel in developing the VLIW Itanium architecture from its own R&D projects (called EPIC), which resulted in the Intel/HP IA64 architecture. Since the early-2000s HP sold two lines of Unix computers and servers in parallel — both PA-RISC 2.0 and Itanium.
- Great Microprocessors of the Past and Present, John Bayko (June 2001/V 12.1.1: BURKS. Accessed 28 Dec 2007)
Floating Point Unit (FPU)
The Floating Point Unit is an assist processor logically added to a system to improve the performance on floating-point operations. The processor can be on a seperate chip (e.g., PA-7000) or integrated onto the central CPU die (all PA-RISC CPUs upwards). The FPU executes special floating point instruction to perform arithmetic on its own set of independent registers (register file) and to move data between its own registers and the system’s lower memory hierarchy. The FPU execution stage is pipelined. All PA-RISC FPUs contain thirty-two 64-bit registers, which can also be used as sixty-four 32-bit registers and sixteen 128-bit registers.
Transition Lookaside Buffer (TLB)
The Translation Lookaside Buffer is a hardware structure doing virtual-to-physical memory address translations. The TLB takes virtual page numbers and returns the corresponding physical page number. The PA-7000 is the last PA-RISC processor to use seperate I/D TLBs, all later PA 1.1 and 2.0 CPUs use a combined TLB structure.
- PA-7000 - 96 I and 96 D entries
- PA-7100 - 120 combined entries
- PA-7100LC - 64 combined entries
- PA-7200 - 120 combined entries
- PA-7300LC - 96 combined entries
- PA-8000 - 96 combined entries
- PA-8200 (PCX-U+) - 120 combined entries
- PA-8500 (PCX-W) - 160 combined entries
- PA-8600 (PCX-W+) - 160 combined entries
- PA-8700 (PCX-W2) - 240 combined entries
- PA-8800 - 2×240 combined entries
- PA-8900 - 2×240 combined entries
Hitachi’s PA-RISC 1.1 derivates also used split TLBs:
- Hitachi PA/50 - 32 I and 64 D entries
- Hitachi HARP-1 - 128 I and 128 D entries (some sources mention a second-level TLB)
Most interestingly, the older PA-RISC 1.0 processors (pre-PA-7000) have huge TLBs (even for today’s standards):
- TS-1 - 4096 entries (split I/D)
- NS-1 - 4096 entries (split I/D)
- NS-2 - 16384 entries (split I/D)
- CMOS26B (PCX) - 8192 entries (split I/D)
The TLB memory on these earlier CPUs was implemented mostly off-chip/off-die via separate memory (SRAM) chips.
PA 1.1: If a virtual address has to be translated to a physical address, the corresponding TLB is searched for an entry matching the Virtual Page number. If an entry is found, the 20-bit Physical Page number, delivered by the TLB, is concatenated with the original 12-bit page offset to the build up the 32-bit absolute physical address.
TLB miss handling implementations
Hardware: If the CPU implementation provides a hardware TLB miss handler, it attempts to find the virtual-to-physical translation in the Page Table. If successful, the translation and protection fields are inserted in the TLB. If not successful, an interruption occurs so the software miss handler can complete the translation.
Software: If software TLB miss handling is implemented, a TLB miss fault interruption routine performs the translation. It inserts the translation and protection fields in the TLB and afterward restarts the interrupted routine, in which the TLB miss occurred.
Block Transition Lookaside Buffer (BTLB)
Similar as the TLB, the BTLB provides virtual-to-physical address translations. However the BTLB maps large address ranges rather that single pages as the TLB does. These large address ranges are called block translations and therefore stored in the Block Translation Lookaside Buffer. These block translations are useful for virtual address ranges that do not get paged in or out.
BTLBs were only implemented on 32-bit PA-RISC processors (PA-7x00), the 64-bit versions instead implement variable page sizes, thus any entry can be of >4k mapping.
A superscalar processor implementation decodes, dispatches and executes multiple instructions per cycle if dependencies between the instructions permit. This is possible if the instruction stream contains independent instructions. Superscalarity can be easily gained from an decoupled floating point unit (FPU) which executes floating point operations (calculations) indepently from the (integer) ALU. More complicated variations allow for parallel load/store operations, integer calculations et al, which need a more complex CPU design that analyzes the instructions/branches.
Every PA-RISC processor from the PA-7100 upwards implements superscalar execution. Instructions proceed together through the execution pipeline which is called instruction bundling. The superscalar execution is functionally transparent to the software, the effects of any given instruction are the same whether it was executed as part of a bundle or alone. Bundling rules are applied at run-time by the hardware; optimal performance may only be gained by proper ordering of the instructions so the processor can use its full superscalar potential.
Several kinds of restrictions are placed upon the instruction bundling:
- Functional unit contention
- Data dependency restrictions
- Control flow restrictions
- Special instruction restrictions
For bundling purposes, all instruction are divided into classes:
|FLOP||Floating point operation|
|LDST||Loads and stores|
|MM||Shifts, extracts, deposits|
|NUL||Might nullify successor|
|BV||Branch Vectored (BV) local, Branch (BE) external|
|FSYS||FTEST and FP status/exception|
|SYS||System control instructions|
PA-7100 superscalar capabilities
The PA-7100 is two-way superscalar with one integer ALU and one FPU.
|Second (younger) instruction|
PA-7100LC/PA-7300LC superscalar capabilities
These are 2-way superscalar processor implementations with two integer ALUs and one FPU. Notably only one of the two ALUs is capable to handle loads, stores and shifts.
|Second (younger) instruction|
Besides from these bundles, LDST + LDST bundles are under certain circumstances also possible. These are then called double word load/store.
Several kinds of instructions cannot be bundled together because of inter-instruction data dependencies:
- An instruction that modifies a register will not be bundled with another instruction that takes
this register as operand.
Exception: a FLOP can be bundled with a FP store of the FLOP’s result register.
- A FP load to one word of a doubleword register will not be bundled with a FLOP that uses the other doubleword of this register.
- A FLOP will not be bundled with a FP load if both instructions have the same target register.
- An instruction that could set the carry/borrow bits will not be bundled with an instruction that uses carry/borrow bits.
- An instruction which is in the delay slot of a branch is never bundled with other instructions.
- An instruction which is at an odd word address and executed as a target of a taken branch is never bundled.
- An instruction which might nullify its successor is never bundled with this successor. Only if the successor is a FLOP instruction this bundle is allowed.
PA-7200 superscalar capabilities
This is a 2-way superscalar processor implementation. It has two integer ALUs and one FPU. Similar to the PA-7100LC, shift-merge and test condition units are not duplicated in the second ALU. To support the superscalar capabilities one additional write port and two additional read ports were added to the general registers (GR*).
|second (younger) instruction|
Multimedia Acceleration eXtensions (MAX-1 and MAX-2)
The original multimedia extensions were proposed for and introduced in the PA-7100LC processor and later also available in the PA-7300LC. The aim was to enable workstations with this CPU to provide real-time MPEG video decompression and playback at a rate of 30 frames/second without the need for a special DSP (digital signal processing) chip.
The design process for the PA-7100LC processor (in the early mid-1990s) included for the first time multimedia benchmarks while analyzing optimizations for the instruction set design.
The actual implementation was achieved via the introduction of a very small
set of SIMD-MIMD1 instructions to faciliate
the application of a small set of instructions on bundled subword data.
Since these instructions use the same data paths and execution units within
the processor as the
normal instructions the term intrinsic signal
processing (ISP) was coined.
By sticking to conventional RISC principles the design team decided against
adding complex special-purpose instructions and opted for small, elegant
use of the existing processing facilities, which just were modified to
understand the new, packed subword data.
In 1994, the extensions made their way to be included in the final PA-7100LC product and as such were the first SIMD1 instructions found in a general microprocessor. Less than 0.2 percent of the silicon area had to be used for these additions and modifications, while allowing a very significant performance boost in affected applications (for example, the then-highend 735/99 workstation running at 99 MHz with 512 KB cache achieves 18.7 fps at MPEG decompression benchmarks, while the new, lower clocked 712 workstation at 60 MHz and with 64 KB cache achieved 26 fps). New MAX-1 multimedia instructions include: parallel add, parallel subtract, parallel shift left & add (i.e. multiply with integer), parallel shift right & add (i.e. division), parallel average.
- Single Instruction Multiple Data, Multiple Instruction Multiple Data (MIMD), see for example the SIMD Wikipedia article and MIMD Wikipedia article
With the introduction of the new 64-bit PA-RISC 2.0 architecture in 1996 HP unveiled a new set of multimedia-oriented instructions aimed at using the processor’s resources more effectively for sub-word data. The basic components of the contemporary multimedia data were often represented as 8, 12 or 16-bit integers, for example audio sampling and pixel color depth. Doing arithmetic with data of this length would waste an considerable amount of the processor’s execution capacities, a simple addition of 16-bit data would only use one quarter of the 64-bit wide integer units datapath. To remedy this situation, MAX allows for packing of these subword data into larger words near the processor’s natural word width (64-bit on PA-RISC 2.0 processors) and using parallel instructions on them. An example would be four 16-bit additions by the 64-bit adder on four 16-bit packed subwords.
The basic functionality from the earlier 32-bit MAX-1 was taken over and four more instructions added for MAX-2. Additionally, due to the wider integer registers (now 64-bit) more subwords can be packed in one cycle, doubling the effective speed of these multimedia instructions. The MAX-2 multimedia instructions include (new in MAX-2 are in bold): parallel add, parallel subtract, parallel shift left & add (i.e. multiply with integer), parallel shift right & add (i.e. division), parallel average, parallel shift right, parallel shift left, mix and permute.
MAX-2 debuted 1996 with the PA-8000 processor and later featured on all subsequent PA-RISC 2.0 processors (PA-8x00). In contrast to contemporary multimedia extensions, MAX-2 required only very little die space (0.1 percent on the PA-8000).
- Accelerating Multimedia with Enhanced Microprocessor (PDF, 2.4 MB)
- Discussion of the MAX-1 instructions. Ruby Lee, April 1995, IEEE Micro, Volume 15 Number 2.
- 64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture (PDF, 66 KB)
- New features of the 64-bit PA-RISC 2.0 architecture and overview on the MAX introduced with it. Ruby Lee and Jerry Huck, 1996, Hewlett-Packard Company.
- Subword Parallelism with MAX-2 (PDF, 1.5 MB)
- Discussion of the MAX-2 instructions. Ruby Lee, August 1996, IEEE Micro, Volume 16 Number 4.
Selected papers and articles for further reading on the PA-RISC architecture and platform
- Hewlett-Packard Precision Architecture: The Processor (.pdf) M. Mahon et al (August 1986: Hewlett Packard Journal. Accessed May 2009)
- PA-RISC 1.1 Architecture and Instruction Set Reference Manual (.pdf) Hewlett-Packard Company (February 1994, third edition. Accessed May 2009 at PA-RISC Linux FTP)
- PA-RISC 2.0 Instruction Set Architecture (.pdf) Hewlett-Packard Company (1995. Accessed May 2009 at PA-RISC Linux FTP)