PA-RISC Processors
Hitachi HARP-1
Overview
The Hitachi HARP-1 is a PA-RISC version 1.1 compatible CPU from Hitachi, introduced in June 1994. It is apparently a larger and faster version of the PA/50 processor, however . not much information is available on either processor.
The HARP-1E variant supposedly includes (pseudo
) vector processing modifications/add-ons
and was used in Hitachi vector/supercomputers.
It seems the L1 cache was increased to 16 KB/16 KB instruction/data.
Details
- PA-RISC version 1.1 32-bit
- Three functional units: two integer ALUs and one floating point unit (and two shift-merge units)
- Six-stage pipeline
- Built-in, pipelined FPU
- Built-in memory controller (Memory Interface Unit, MIU)
- 2-way superscalar
- L1 I cache: 8 KB, 1-way set-associative, 32-byte blocks
- L1 D cache: 16 KB, 2-way set-associative, 32-byte blocks, copy-back
- L1 caches are on-chip
- L2 I/D 512/512 KB, off-chip
- TLB: I/D 128/128-entry, 1-way set
- (Some say a second level TLB was included)
- L2 Cache bus: 128-bit (ECC) data path to L2 caches
- Processor bus: 64-bit (parity) data path to main memory and I/O
- Up to 150 MHz frequency with 3.3 V core voltage, 17W power dissipation (at 120 MHz)
- 16.2×16.5 mm2 die, 2,800,000 FETs, 0.5µ (micron) 3-layer aluminium + 1-layer tungsten BiCMOS, packaged in 595-pin PGA
Used in
- Hitachi SR2201 supercomputer (HARP-1E)
- Probably others
References
- Chronology of Workstation Computers (1993) Ken Polsson (November 2007. Accessed November 2007)
- PROgress (PA-RISC) Newsletter - comp.sys.hp Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
- Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (PDF) Hidekazu Terai et al (October 1999: Hitachi Ltd. Accessed January 2008)
- A 120- MHz BiCMOS Superscalar RISC Processor, Shigeya Tanaka et al (IEEE Journal of Solid-State Circuits, vol. 29, no. 4, April 1994)