PA-RISC Processors

Hitachi PA/50

Overview

The Hitachi PA/50 is a PA-RISC version 1.1 compatible processor designed and manufactured by Hitachi, released in 1993. Two designs were developed: M and L (L for low-cost). They were used as personal workstation processors and high-end embedded controllers. Hitachi integrated a set of features previously not implemented at that time in other PA-RISC processors, e.g., on-chip caches, data-prefetching, a power-saving mode and SDRAM support.

Details

PA-RISC version 1.1 32-bit
Built-in, pipelined FPU
L1 I: 8 KB, 2-way set-associative, 32-byte blocks
L1 D: 4 KB, 2-way set-associative, 32-byte blocks, copy-back
L1 caches are on-chip
Uncacheable memory (per page)
TLB: I/D 32/64-entry, 2-way set, 4K-page, each +2 additional block entries
BTLB (256 KB-32 MB)
Seven 32-bit shadow registers for fast interrupts
Data-prefetching
Non-blocking cache
Power-saving mode, reducing frequency to 1/8
Support for SDRAM
PA/50L: Up to 33 MHz frequency with 3.3 V core voltage
PA/50M: Up to 60 MHz frequency with 5.0 V core voltage
11.5×12.0 mm² die, 1,280,000 FETs, 0.6µ (micron), 3-layer metal CMOS packaged in a 160-pin plastic QFP package

Used in

Hitachi 3050RX 100C, 200

References

PROgress (PA-RISC) Newsletter - comp.sys.hp: Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)

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