PA-RISC Processors

Other PA-RISC processors

Various processor and controller vendors implemented embedded PA-RISC solutions, both geared for set-top boxes (TVs, DVRs etc.) and for device controllers (printers). A common feature is the integration of various I/O functions onto the processors/controller chip, such as memory, PCI and serial/parallel.

Other PA-RISC processors overview
CPU	ISA	Clock max	FETs	Cache	Bus	Super scalar	Units	Controllers on-chip
Winbond W89K	PA 1.1 32-bit	33/66 MHz	1.1M	2/2 KB I/D on-chip L1	Intel 486	1-way	1 Integer	none?
Winbond W90210 W90215	PA 1.1 32-bit	33/66 MHz	?	4/8 KB I/D on-chip L1	Intel 486	1-way	1 Integer MAX-1	DRAM DMA PCI I/O
Winbond W90220 W90221	PA 1.1 32-bit	150 MHz	?	4/4 KB I/D on-chip L1	Intel 486	1-way	1 Integer 1 MAC(DSP) MAX-1	DRAM DMA PCI IDE I/O VGA (W90221) TV (W90221)
Oki OP32	PA 1.1 32-bit	33 MHz	1.1M	?	?	1-way	1 Integer	DRAM DMA

Winbond W89K

The Winbond W89K is an embedded 32-bit PA-RISC controller chip, pin-compatible with the then-popular Intel 80486DX, introduced in Spring 1994. It could be used as a drop-in replacement in mid-1990s PCs together with Winbond BIOS replacement chips. Rationale was to allow hardware developers utilize existing 486DX mainboards and components for a shorter product development process. The W89K is a level 0 PA-RISC 1.1 implementation: a 32-bit PA-RISC processor without virtual addressing.

PA-RISC version 1.1 (third edition) 32-bit
Level 0 implementation (no virtual addressing): no MMU
Five-stage pipeline
One functional unit: one 32-bit integer ALU
2 KB/2 KB I/D on-chip L1 caches
80486 (Intel) bus interface
33 MHz and 66 MHz clock speeds were available, with the latter apparently having been achieved with a clock-doubling also used in the Intel’s 80486DX/2 (the chips uses an internal clock-doubler on the external 33 MHz bus)
On-chip JTAG support
14.3×14.3 mm² die, 1,100,000 FETs, 0.8µ (micron), 3-layer metal CMOS

References

PROgress (PA-RISC) Newsletter - comp.sys.hp: Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
Winbond, Varian sign deal for thin-film IC process: Terho Uimonen (April 1994: Electronic News. Accessed January 2008 at findarticles.com)
PA-RISC in a PC box (was: Re: HP's vision of a low-end 3000) - comp.sys.hp.mpe: Stan Sieler (Februar 1996. Accessed December 2007)

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Winbond W90210/215

Shortly after the W89K embedded controllers Winbond introduced more sophisticated PA-RISC processors in Fall 1997 with the W90K line of embedded controllers. The W90210F still was 32-bit PA-RISC 1.1 but integrated many external I/O components on the chip — DRAM and DMA controllers, a PCI bridge and various I/O ports. As its predecessor, the W90210F was a level 0 PA-RISC 1.1 implementation without virtual addressing. It was apparently used in various Internet appliances: set-top boxes, TV sets, DVD players, PDAs, VoIP devices, and for industrial automation. The W90215 is identical to the W90210 but did not include license rights for the embedded operating system (and was thus cheaper).

PA-RISC version 1.1 (third edition) 32-bit
Level 0 implementation (no virtual addressing): no MMU
Five-stage pipeline
One functional unit: one 32-bit integer ALU
L1 I cache: 4 KB, direct mapped, 32-byte blocks, 256 entries
L1 D cache: 8 KB, 2-way set-associative, 32-byte blocks, 2×64 entries, write-back
MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG decoding
80486 (Intel) bus interface
DRAM controller
ROM/FLASH interface
DMA controller (2-channel 8-bit)
PCI bridge
Two serial ports
Parallel port
33 MHz and 66 MHz clock speeds (?)
208-pin PQF package

References

W90210F PA-RISC Embedded Controller (.pdf): Winbond Electronics Corp. (October 1997. Accessed January 2008)

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Winbond W90220 and W90221

The W90220F is, as its predecessor W90210, a 32-bit PA-RISC 1.1 design without MMU but integrated many external I/O components on the chip — DRAM and DMA controllers, PCI bridge, IDE channels, I/O ports and, on the W90221, a graphics/TV chip. Released in Spring 1999, it had the same target systems of set-top boxes and internet appliances. The sucessor W90221 is apparently similar, with higher clock speed, integrated (S)VGA and TV controller

PA-RISC version 1.1 (third edition) 32-bit
Level 0 implementation (no virtual addressing): no MMU
Six-stage pipeline
Two functional units: one 32-bit integer ALU and one 32-bit multiply-accumulate (MAC) module (for DSP purposes, can be used as two 16-bit modules too)
L1 I cache: 4 KB, direct mapped, 32-byte blocks, 256 entries
L1 D cache: 4 KB, 4-way set-associative, write-back or write-through
MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG decoding
80486 (Intel) bus interface
Hardware dynamic branch prediction
256-entry branch-target-buffer (i. e. BTAC)
Memory controller (supports DRAM, EDO-DRAM and SRAM; W90221 additionally SDRAM)
ROM/FLASH interface
DMA controller (2-channel 8-bit)
IDE I/O controller (four 16-bit channels)
W90221: VGA and TV controller (W9971)
PCI bridge
Two serial ports
Parallel port
Serial ICE port
Up to 150 MHz clock speed at 3.3 V/5 V I/O and 3.3 V core
W90221: 133 MHz clock speed with apparently 3.3 V at both I/O and core
0.35µ (micron) single-poly-triple-metal CMOS
208-pin PQF package

References

W90220F PA-RISC Embedded Controller (.pdf): Winbond Electronics Corp. (March 1999. Accessed January 2008)

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Oki OP32

Oki Semiconductor OP32/50N was introduced in 1994 as an embedded controller, based on a 32-bit PA-RISC design with integrated DRAM and DMA controllers. The chip was targeted at laser printers, Fax machines, X-Terminals and the Telecom and Automotive markets.

PA-RISC version 1.1 32-bit
33 MHz frequency
14.3×14.3 mm² die, 1,100,000 FETs, 0.8µ (micron), 3-layer metal CMOS

References

PROgress (PA-RISC) Newsletter - comp.sys.hp: Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)

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