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PA-RISC Processors

PA-7100/PA-7150 (PCX-T)

Overview

The PA-7100 was the first PA-RISC CPU to integrate the ALU and FPU on a single die, saving board space and lowering production cost. It was introduced in 1992, with the enhanced PA-7150 being added in 1994. The design of the integer units is close to the PA-7000, which was modified to scale to higher frequencies; the (previously external) FPU was newly designed, taking about one third of the transistor count. The link between the PA-7100 and its instruction cache was doubled compared to the PA-7000, which enables the CPU to fetch multiple consecutive instructions and simultaneously dispatch them to independent integer and floating point units. The PA-7100 is a superscalar processor that is able to issue two separate instructions at a time.

SMP systems can be built with two alternative strategies: either two PA-7100s attach via a shared PBus to one Memory and I/O Controller (Viper) to which the system bus and memory separately attach; or each PA-7100 is attached to its own MIOC, which in turn is attached to a shared memory and I/O bus with the other PA-7100/MIOCs.

The PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up to 125 MHz.

Details

Used in

References

  1. A 200 MFLOP HP PA-RISC Processor (.pdf) W. Jaffe, B. Miller, J. Yetter (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV)
  2. Multiprocessor Features in a PA-RISC Processor Interface Chip (.pdf) T. Alexander et al (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV)
  3. Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)

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