PA-RISC Processors

PA-7100/PA-7150 (PCX-T)

Overview

The PA-7100 was the first PA-RISC CPU to integrate the ALU and FPU on a single die, saving board space and lowering production cost. It was introduced in 1992, with the enhanced PA-7150 being added in 1994. The design of the integer units is close to the PA-7000, which was modified to scale to higher frequencies; the (previously external) FPU was newly designed, taking about one third of the transistor count. The link between the PA-7100 and its instruction cache was doubled compared to the PA-7000, which enables the CPU to fetch multiple consecutive instructions and simultaneously dispatch them to independent integer and floating point units. The PA-7100 is a superscalar processor that is able to issue two separate instructions at a time.

SMP systems can be built with two alternative strategies: either two PA-7100s attach via a shared PBus to one Memory and I/O Controller (Viper) to which the system bus and memory separately attach; or each PA-7100 is attached to its own MIOC, which in turn is attached to a shared memory and I/O bus with the other PA-7100/MIOCs.

The PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up to 125 MHz.

Details

PA-RISC version 1.1b 32-bit
Two functional units: 1 integer ALU, 1 Floating Point unit
2-way superscalar
SMP-capable
CPU, FPU, MMU and cache controller on one chip, memory and I/O controller (Viper MIOC) off-chip
Five-stage pipeline
Pipeline store technique for reduction of penalty for execution of any store to data cache
Stall-on-use mechanism for parallel procession of instruction streams and cache misses
3-instruction queue
Hardware TLB miss handler
Hardware static branch support
I/D cache bypass (7150)
Off-chip L1 caches up to 1 MB I and 2 MB D realized in asynchronous standard SRAMs
I/D caches are both 64-bit per access, direct mapped, parity protected and cycled at CPU clock
Caches are attached directly to the CPU
Caches are software accessible
Caches are virtually indexed and physically tagged to minimize latency
120-entry fully associative TLB
16-entry BTLB with programmable page sizes up to 64 MB
CPU attaches via PBus to the Viper memory and I/O controller (MIOC)
PBus is 32-bit multiplexed address/data bus and probably runs at possible bus speeds of 1.0, .67 and .50 of processor speed
Two different multiprocessing connection strategies supported (shared MIOC or dedicated MIOCs)
MP cache coherency support
Up to 100 MHz frequency (PA-7100) with 5.0 V core voltage
Up to 125 MHz frequency (PA-7150) with 5.0 V core voltage
14.0×14.0 mm² die, 850,000 FETs, 0.8µ (micron), 3-layer metal CMOS (CMOS26B process) packaged in a 504-pin ceramic PGA package
Power dissipation of 30W at 100 MHz

Used in

References

A 200 MFLOP HP PA-RISC Processor (.pdf) W. Jaffe, B. Miller, J. Yetter (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV)
Multiprocessor Features in a PA-RISC Processor Interface Chip (.pdf) T. Alexander et al (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV)
Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)

↑ up

← back to processors