PA-RISC Processors

PA-7100LC (PCX-L)

Overview

The PA-7100LC, introduced 1994, was primarily designed as a single-chip solution for low cost systems while still delivering the performance of 1991 high-end workstations and servers. The CPU core design is close to the earlier PA-7100 and was integrated with several previously off-chip support components (FPU, MIOC, first-level cache) onto a single chip with direct GSC main bus attachment. Both CPU and FPU are 32-bit PA-RISC 1.1.

The successor of the PA-7100LC is the similar but improved PA-7300LC processor, released two years later.

Details

PA-RISC version 1.1c 32-bit
Three functional units: 2 integer ALUs, 1 Floating Point unit1
2-way superscalar
Not SMP-capable
Five-stage pipeline
DRAM memory & cache controller (MIOC) integrated on die, thus direct interface from the CPU to memory and cache
1 KB on-chip I L1 instruction cache, direct mapped, 64-bit per access, prefetch from off-chip I cache
8 KB-2 MB off-chip unified I/D L1 cache, direct mapped, hashed address, virtual index, 480-600 MB/s bandwidth
The 1 KB on-chip I cache is not really considered a true cache, thus the off-chip cache in fact is the system’s real L1 cache
32-Byte cache line size
Support for bi-endian load-store operations
MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG decoding
Floating Point load-store to I/O space
64-entry unified I/D TLB, fully associative, 4K page size
8-entry BTLB, page sizes from 512K - 64M
64-bit wide load/store operations
I and D cache bypassing
Stall on use D cache miss policy
Don’t fill on miss cache hint
Hardware TLB miss handler support
Hardware static branch prediction
GSC bus interface
64-bit ECC interface to the main memory
Instruction line prefetch from main memory
Up to 100 MHz clock
14.2×14.2 mm² die, 900,000 FETs, 0.75µ (micron), 3-layer aluminium process packaged in a 432-pin PGA

Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition or multiplication. Both units can handle branch operations.

Used in

References

PA7100LC ERS (External Reference Specification) (.pdf) Hewlett-Packard Company (1999)
The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment Mick Bass et al (April 1995: Hewlett-Packard Journal. Accessed May 2009)
Design methodologies for the PA 7100LC microprocessor (.pdf) Mick Bass et al (April 1995: Hewlett-Packard Journal. Accessed May 2009)

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