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PA-RISC Processors

PA-7200 (PCX-T')

Overview

The PA-7200 completely revised the PA-7100 processor core, leveraging only the FPU in its release in early 1995. Being a two-way superscalar processor, the PA-7200 can dispatch and execute two separate instructions at a time to its functional units. In contrast to the PA-7100 it has two separate integer ALUs and thus can execute two ALU integer operations simultaneously. Other changes include a redesigned cache architecture — while retaining the general cache layout with large off-chip L1 caches at CPU clock speed — and use of the Runway processor bus, carried on to later PA-8x00 processors. The PA-7200 was targeted towards high-performance general-purpose applications, but also on specialized applications with large working sets which could take advantage of the high-bandwidth bus interface.

Details

Used in

References

  1. Design of the HP PA 7200 CPU (.pdf) Kenneth K. Chan et al (February 1996: Hewlett-Packard Journal) (mirror: Design of the HP PA 7200 CPU)
  2. Verification, Characterization, and Debugging of the HP PA 7200 Processor (.pdf) Thomas B. Alexander et al (February 1996: Hewlett-Packard Journal)
  3. A Different Kind of RISC Dick Pountain (August 1994: BYTE Journal)
  4. Interview with David Fotland, September/October 2008

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