The PA-7300LC is an integrated,
low-cost PA-RISC 32-bit processor, released in mid-1996.
While being a close successor to the earlier PA-7100LC,
it has several enhancements:
- Large on-chip L1 caches, in contrast to the small
assistcaches of the PA-7100LC and PA-7200.
- Integrated L2 cache controller in the MIOC.
- Improved bus interface with faster GSC bus variant.
- Faster memory interface.
The then current process technologies made it possible to include a large L1 cache on the CPU die, breaking a long-standing HP tradition of large off-chip L1 caches. The PA-7300LC was the final 32-bit, PA-RISC version 1.1 CPU, later workstations and servers used 64-bit PA-RISC 2.0 processors, such as the PA-8000, being introduced in the same timeframe.
- PA-RISC version 1.1e 32-bit
- Three functional units: 2 integer ALUs, 1 Floating Point unit1
- 2-way superscalar
- MAX-1 multimedia extensions (subword arithmetic) for multimedia applications (not explicitly mentioned on the PA7300LC, but its documentation states support for MAX-1 instructions)
- 64 KB/64 KB I/D on-chip L1 caches, each two-way set associative, virtually indexed
- Cache line size of 32 Byte
- Caches have a 64-bit datapath to the execution units, 256-bit datapath to main memory
- Optional unified I/D L2 off-chip cache, up to 8192 KB
- No hashing for both I and D caches
- L2 cache is write-through, direct mapped, physically indexed and physically tagged
- Instruction prefetch buffer moved from memory controller to L1 instruction cache, thus allowing prefetch hits without penalty
- On-chip MIOC memory controller
- 96-entry unified I/D TLB
- 8-entry BTLB
- 4-entry ILAB
- GSC system interface (implements GSC+ features), maximum clock frequency of 40 MHz — actual system implement from 33 MHz (132 MB/s), 36 MHz (140 MB/s) and up to 40 MHz (160 MB/s)
- Either 64-bit or 128-bit datapath from execution units to the memory
- Up to 180 MHz frequency with 3.3 V core voltage
- 15.3×17.0 mm2 die, 9,200,000 FETs, 0.5µ (micron), 4-layer metal CMOS (CMOS14C process) packaged in a 464-pin ceramic PGA package
- Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition o multiplication. Both units can handle branch operations.
- 744, 745, 748
- A180, A180C
- B132L, B132L+, B160L, B180L+
- C132L, C160L
- D220, D230, D320, D330
- RDI PrecisionBook
- Hitachi 3050RX 255, 355E, 365
- PA7300LC ERS (External Reference Specification) (PDF, 716 KB) Hewlett-Packard Company (1996)
The PA-7300LC: the first
System on a Chip(archive.org mirror) Tom Meyer (1996: Presentation for Microprocessor Forum 1995)
- The PA 7300LC Microprocessor: A Highly Integrated System on a Chip (PDF, 50 KB) Terry W. Blanchard and Paul G. Tobin (June 1997: Hewlett-Packard Journal)