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PA-RISC Processors

PA-8000 (PCX-U)

Overview

The PA-8000 is the first 64-bit PA-RISC processor with out-of-order (OoO) execution capabilities, released in 1996. It has four integer, four floating-point and dual load/store units, a large OoO dispatch window and no on-chip caches. The PA-8000 is the first chip to implement the 64-bit PA-RISC 2.0 architecture with extensions to support 64-bit computing. This includes 64-bit wide integer registers and functional units (ALU, shift/merge) and a flat (virtual) address space of 64-bit. (PA-RISC 2.0 processors support only a physical address space/addressable physical memory of between 40-bit/1 TB and 44-bit/16 TB.) Other extensions in the PA-8000 include fast TLB insert instructions, memory prefetch instructions, support for variable sized pages, branch prediction hinting and new FPMAC (Floating Point Multiply Accumulate) units.

A key feature of the PA-8000 and all later PA-RISC 2.0 processors is the IRB (Instruction Reorder Buffer), which enables the processor to perform its own instruction scheduling in hardware, independent of compiler or other software technologies. The IRB can store up to 28 computation and 28 load/store instructions; it tracks interdepencies between these instructions and allows execution as soon as they are ready. Also tracked are branch prediction outcomes and with re-scheduling the CPU can execute instructions past cache misses. The IRB is the key part in the OoO execution capabilities of the chip.

All later PA-8x00 processors include only slightly modified PA-8000 core(s) as CPU and only extend support and cache logic.

Details

Used in

References

  1. Advanced Performance features of the 64-bit PA-8000 (archive.org mirror) Doug Hunt (1995: IEEE CompCon 5)
  2. PA-8000 Combines Complexity and Speed (archive.org mirror) Linley Gwennap (1994: Microprocessor Report, Volume 8 Number 15)
  3. Four-Way Superscalar PA-RISC Processors (.pdf) Anne P. Scott et al (August 1997: Hewlett-Packard Journal)
  4. The HP PA-8000 RISC CPU A High Performance Out-of-Order Processor (.pdf) [link gone] Ashok Kumar (August 1996: IEEE Hot Chips VIII)

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