Shortly after the introduction of the PA-8000 the design team noted several aspects of this chip for improvement in the successor, which were corrected with the PA-8200 in 1997.
- Branch prediction
- TLB miss rates
- Cache sizes
The new chip should offer improved performace, compatibility with existing applications and short time to market,
with the whole design heavily leveraged from the existing PA-8000 foundation.
The availability of new 4 Mb SRAMs with faster access times allowed for an increased CPU clock speed and bigger caches.
Smaller changes include an increase to the BHT and TLB as
high benefit, low risk improvements.
- PA-RISC version 2.0 64-bit
- Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
- 4-way superscalar
- Two address adders
- External memory and I/O controllers
- 120-entry fully-associative dual-ported TLB
- 42-entry BTAC (Branch Target Address Cache)
- 1024-entry BHT (Branch History Table)
- Dynamic and static branch prediction modes
- Off-chip L1 caches up to 2 MB I and 2 MB D, realized in synchronous 5ns (200 MHz) late-write 4 Mb SRAMs, one cycle latency
- Caches are direct-mapped and dual-ported
- 56-entry instruction queue/reorder buffer (IRB)
- Each instruction includes five predecode bits
- MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG decoding
- Bi-endian support
- Runway system/memory bus, 120 MHz, 64-bit wide, featuring split transactions and glueless multiprocessing. Max. throughput of 960 MB/s
- CPU interfaces to UTurn I/O adapters and MMC/SMC memory controllers on the Runway bus
- Up to 300 MHz frequency with 3.3 V core voltage
- 17.7×19.6 mm2 die, 4,500,000 FETs, 0.5µ (micron), 5-layer metal CMOS packaged in a 1,085-pin flip-chip LGA package
- Four-Way Superscalar PA-RISC Processors (PDF, 190 KB) Anne P. Scott et al (August 1997: Hewlett-Packard Journal)
- HP Pumps Up PA-8x00 Family (archive.org mirror) Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14). [Article reprint for cpu.hp.com]
- HP's Latest PA-RISC Microprocessor Evolution Enables 50 Percent Application Performance Boost Hewlett-Packard (October 1996: HP press release). [Article mirror for hp.com]