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PA-RISC Processors

PA-8500 (PCX-W)

Overview

The PA-8500 processor is the direct evolution of the PA-8000 and PA-8200 processors, taking over a very similar processing core but implementing large on-die L1 caches. This chip, introduced in September 1998, marked a first for PA-RISC processors and a break with the long-standing HP tradition of keeping large L1 caches off-chip. (The two years older PA-7300LC also includes on-chip L1 caches, albeit much smaller). There were no other significant changes to the processing core, besides small increases to the TLB and BHT.

The main challenge in the PA-8500 development were the large on-chip L1 caches, which had to fit onto the allocated die area and be able to keep up with the instruction reordering in the IRB. The data cache is composed of 0.5 MB banks, implemented with four 0.125 MB arrays providing error correction. The instruction cache is implemented as one bank of 0.5 MB four-way set associative pipelined cache, providing 128 bits of instruction per cycle plus pre-decode bits.

Details

Used in

References

HP Pumps Up PA-8x00 Family (archive.org mirror)
Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14). [Article reprint for vanished cpu.hp.com]
A 500  MHz 1.5  MByte Cache with On-Chip CPU (PDF, 141 KB)
Jonathan Lachman and J. Michael Hill (1997: ISSCC).
PA-8500: The Continuing Evolution of the PA-8000 Family (archive.org mirror)
Gregg Lesartre and Doug Hunt (1997: Proceedings of CompCon, IEEE CS Press). [Article reprint for vanished cpu.hp.com]

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