PA-RISC Processors

PA-8600 (PCX-W+)

Overview

The PA-8600 is a PA-8500 with minor modifications for a new manufacturing process in order to achieve higher clock speeds, which was the main aim of developing the PA-8600, released in January 2000. One of the few changes to the original design is a quasi LRU replacement policy for the instruction cache.

Details

PA-RISC version 2.0 64-bit
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
4-way superscalar
Two address adders
SMP-capable
External memory and I/O controllers
160-entry fully-associative dual-ported TLB
32-entry BTAC (branch target address cache)
2048-entry BHT (branch history table)
Dynamic and static branch prediction modes
On-chip L1 caches 0.5 MB I and 1 MB D, each 4-way set associatve
32 or 64 Byte cache line size
Supports up to 1 TB of physically addressable memory (40-bit physical addresses)
56-entry instruction queue/reorder buffer (IRB)
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG decoding
Quasi LRU replacement policy for the instruction cache
Bi-endian support
Runway+/Runway DDR system/memory bus, 125 MHz, 64-bit, DDR (double data rate), about 2.0 GB/s peak bandwidth
CPU interfaces in smaller systems to the Astro memory and I/O controller, in larger/mainframe systems to the DEW Runway ports/converters of the Stretch chipset or to the Cell chipset (probably with converters, since Cell is also an Itanium chipset)
Up to about 550 MHz frequency with 2.0V core voltage
21.3×22.0 mm² die, 140,000,000 FETs, 0.25µ (micron), 5-layer metal CMOS packaged in a 544-pin LGA package

Used in

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