PA-RISC Processors

PA-8700 (PCX-W2)

Overview

The PA-8700 is an enhanced PA-8500 core with several modifications, released in August 2001. As with all PA-8x00 processors the logic core of the PA-8700 is still very close to the original PA-8000 core from 1997. All subsequent PA-RISC processors from HP were based on this basic PA-RISC version 2.0 design while adding features and slight modification. The PA-8700 significally enhanced the on-chip L1 caches and TLB while switching to a new manufactoring process helped increasing the clock speed. The PA-8700 was at its time one of the largest available commercial processors and one of the first manufactured in a SOI (Silicon On Insulator) process. After the Intel-fabbed PA-8500 and PA-8600 , the PA-8700 was produced in IBM’s fabs after HP gave up its own in the 1990s.

Details

PA-RISC version 2.0 64-bit
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
4-way superscalar
Two address adders
SMP-capable
External memory and I/O controllers
240-entry fully-associative dual-ported TLB
32-entry BTAC (branch target address cache)
2048-entry BHT (branch history table)
Dynamic and static branch prediction modes
0.75 MB I and 1.5 MB D on-chip L1 caches, each 4-way set associatve, implemented in independent 0.75 MB banks.
32 or 64 Byte cache line size
Data cache prefetching
Quasi LRU replacement policy for both the instruction and data cache.
Supports up to 16 TB of physically addressable memory (44-bit physical addresses)
56-entry instruction queue/reorder buffer (IRB)
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG decoding
Bi-endian support
Support for hardware lock-stepping, i.e. operating multiple chips in parallel to detect faults
Runway+/Runway DDR system/memory bus, 125 MHz, 64-bit, DDR (double data rate), about 2.0 GB/s peak bandwidth
CPU interfaces in smaller systems to the Astro memory and I/O controller, in larger/mainframe systems to the DEW Runway ports/converters of the Stretch chipset or to the Cell chipset (probably with converters, since Cell is also an Itanium chipset)
Up to 750 MHz (875 MHz on the PA-8700+) frequency with 1.5 V core voltage
16.0×19.0 mm² die, 186,000,000 FETs, 0.18µ (micron), 7-layer Silicon-on-Insulator CMOS packaged in a 544-pin LGA package

Used in

References

A 900 MHz 2.25 MByte Cache with On Chip CPU (PDF, 119 KB) J. Michael Hill and Jonathan Lachman (2000: ISSCC)
PA-RISC 2.0 Architecture (.pdf) Hewlett-Packard Company (1995)

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