PA-RISC Processors

Early PA-RISC

The first PA-RISC processors were designed and used in mid to late-1980s in HP 9000/800 servers (and HP 3000 MPE/iX systems). The exact naming scheme is not really clear as one group of sources refers to them as TS-1, NS-1 and NS-2 while others call apparently the same processors PN-5, PN-7 and PN-10. These early CPUs still mostly were chipsets with multiple separate chips and components forming the central processing unit, contrary to the mostly single-chip post-PA-7000 implementations. The chips were based on TTL, then NMOS-III and finally CMOS26B. An interesting aspect of these CPUs are their huge TLB sizes — from 2048 up to 16384 entries while their successors and competitors had sizes typically in the low to mid hundreds.

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TS-1

The TS-1 was the first PA-RISC production processor, introduced in 1986. It integrated version 1.0 of PA-RISC on six boards (each 8.4×11.3″) of TTL.

Details:

PA-RISC version 1.0 32-bit
Three-stage pipeline
The CPU consists of six separate boards:
1. I-unit: the Instruction Unit
2. Register File Board, contains general and control registers
3. E-unit: the Execution Unit
4. TLB, the translation lookaside buffer with 4096 entries for 2 KB pages
5. Cache controller with split instruction and data caches — 64 KB for each I and D
6. FPC, the floating-point coprocessor, handles FP operations parallel to the CPU/ALU (the ADD/MUL/DIV chip was taken over from the HP 9000/550 FOCUS system)
4096-entry TLB off-chip, direct-mapped
Off-chip L1 cache of 128 KB (I/D) direct-mapped/one-way associative
Physical address space of 27-bit (128 MB main memory could be addressed)
8 MHz clock speed
Six (some sources say five) printed circuit boards, implemented in FAST TTL and (25ns and 35ns) SRAMs/PALs, which each about 150 ICs

Used in: 840

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NS-1

The first implementation of PA-RISC in a NMOS fabrication process followed in 1987, shortly after the original TTL-based TS-1, and was called NS-1. The NS-1 processor is integrated on one circuit board (two on 825 server) with the CPU as single NMOS-III chip supplemented by external support chips:

Details:

PA-RISC version 1.0 32-bit
Three-stage pipeline
CPU is a single chip, with eight support VLSI chips
1. SIU (system interface unit), attaches the CPU to the SMB main bus
2. two CCUs (cache controller units CCU0 and CCU1), attach to separate external cache chips
3. TCU (TLB controller unit), attaches to the external TLB chips
4. MIU (math interface unit), controls three third-party floating point (FP) chips (ADD, MUL and DIV)
2048 to 4096-entry TLB off-chip
Off-chip L1 cache of 16 KB (HP 9000/825) to 128 KB (others), unified
Physical address space of 29-bit (512 MB main memory could be addressed)
CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
25-30 MHz clock speed
One circuit board (two boards on HP 9000/825), 144,000 FETs, implemented in NMOS-III packaged in a 272-pin ceramic PGA package

Used in: 825, 835, 850

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NS-2

The final NMOS PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 introduced in 1989-90 with increased pipeline stages (from three to five), new TLB and cache controllers and significantly larger caches and TLB. The NS-2 design was simplified over its NS-1 predecessor. The processor is implemented on one circuit board with the CPU as a single NMOS-III and seven other VLSI chips. The bus structure connecting these chips was updated and simplified, with the CPU having private connections to the cache and TLB controllers (for which the NS-1 CPU had to use the shared cache bus).

Details:

PA-RISC version 1.0 32-bit
CPU is a single chip with seven VLSI support chips
1. SIU (system interface unit), attaches the CPU to the SMB main bus
2. two CCUs (cache controller units, split into instruction and data — ICCU and DCCU), attach to separate external cache chips
3. TCU (TLB controller unit), attaches to the external TLB chips
4. FPC (floating point controller), controls two third-party floating point (FP) chips (ADD, MULTI)
Five-stage pipeline
16384-entry TLB off-chip
Off-chip L1 cache up to 1024 KB, split into I/D
Physical address space of 29-bit (512 MB main memory could be addressed)
CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
27.5 MHz clock speed (or maximum of 30 MHz?), power dissipation of 26W
One circuit board, CPU implemented in NMOS-III, 183,000 FETs, 1.5µ NMOS-III, die size 14.0×14.0 mm² die, packaged in 408-pin PGA

Used in: 822, 832, 845, 855, 860

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PCX (CMOS26B)

The last PA-RISC 1.0 design was the PCX, introduced 1990 and the first PA-RISC processor fabricated in a CMOS process. It implemented the NS-1/NS-2 NMOS design and several of the processor functions previously supplied on external VLSI chips onto a single CPU chip. The PCX still was supplemented by external support chips, including three CMUX (cache multiplexer — one instruction, two data; equivalent to the earlier CCUs), SPI (SMB to processor interface — SMB is the system main bus), FPC (floating point coprocessor) and two FP chips (MUL/DIV and ADD/SUB) [not completely clear if the latter two or latter three chips are third-party].

PA-RISC version 1.0 32-bit
First multi-processor-capable PA-RISC CPU (up to four-way SMP)
Direct predecessor of the PA-7000 (PCXS) processor which integrated most processor logic minus the FPU onto a single die/chip
External FPU (apparently ECL logic)
8192-entry TLB on-chip
Off-chip L1 cache up to 1024 KB, split into I/D (apparently asymmetrical 1:2 I/D)
Physical address space of 29-bit (512 MB main memory could be addressed)
CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
50 MHz clock speed
One circuit board, 196,000 FETs, 1.0µ (micron), implemented in three-level CMOS (CMOS26B)
CPU is a single chip, needs seven other (VLSI) support chips for memory/bus interfaces and I/O

Used in: 842, 852, 865, 870

There are sources which also mention a CS-1 processor — from the nomenclatura this would point to a CMOS design but the performance figures/charts do not really match up with the CMOS26B/PCX described here.

References

Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture (January 1988: Software Research Northwest Inc.)
Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal)
HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008 at hpmuseum.net)
HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008 at hpmuseum.net)
HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008 at hpmuseum.net)
New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com)
HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008 at hpmuseum.net)
A 30 MIPS VLSI CPU, Brian D. Boschma et al (ISSCC 89: February 1989)

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