OpenPA.net

PA-RISC Processors

Introduction

The PA-RISC platform is based on RISC processors from HP and was used in HP computers from the 1980s to the mid-2000s. Three major revisions of the PA-RISC architecture were developed:

  1. PA-RISC 1.0 (32-bit) implemented in several early processors and used in the very first PA-RISC servers in the 1980s (no MMU): NS-1, NS-2 and PCX.
  2. PA-RISC 1.1 (32-bit) used in HP 9000 servers and workstations from the late-1980s and 1990s: the first PA-7000 and PA-7100 and the later integrated low-cost PA-7100LC and PA-7300LC.
  3. PA-RISC 2.0 (64-bit) extended PA-RISC to 64-bit with a redesign of most parts of the architecture, used in the late-1990s to 2000s in the last PA-RISC computers: PA-8000 and PA-8200 (very similar) and the modified iterations PA-8500, PA-8600 and PA-8700 with large on-chip caches. PA-8800 and PA-8900 are dual-core chips, with the last PA-9000 never implemented.

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HP PA-RISC CPUs

The following PA-RISC processors have been developed and used by HP throughout the years.

HP PA-RISC processors overview
CPU ISA Release Clock
MHz
FETs L1 Cache
MB max
L2 Cache
MB max
Bus Super
scalar
SMP Units
TS-1 PA 1.0
32-bit
1986 8 ? 0.125
off-chip
  Custom 1-way 1 Integer
External FPU
NS-1 PA 1.0
32-bit
1987 30 144k 0.125
off-chip
  SMB 1-way 1 Integer
External FPU
NS-2 PA 1.0
32-bit
1989 27.5 183k 1
off-chip
  SMB 1-way Yes 1 Integer
External FPU
PCX PA 1.0
32-bit
1990 50 196k 1
off-chip
  SMB 1-way Yes 1 Integer
External FPU
PA-7000 PA 1.1a
32-bit
1991 66 577k 0.5
off-chip
  PBus/VSC 1-way 1 Integer
External FPU
PA-7100
PA-7150
PA 1.1b
32-bit
1992 125 850k 3
off-chip
PBus/VSC 2-way Yes 1 Integer
1 Floating Point
PA-7100LC PA 1.1c
32-bit
1994 100 900k 0.001
on-chip
2
off-chip
GSC 2-way 2 Integer
1 Floating Point
MAX-1
PA-7200 PA 1.1d
32-bit
1995 140 1.3M 0.002
on-chip
3
off-chip
Runway 2-way Yes 2 Integer
1 Floating Point
PA-7300LC PA 1.1e
32-bit
1996 180 9.2M 0.125
on-chip
8
off-chip
GSC 2-way 2 Integer
1 Floating Point
MAX-1
PA-8000 PA 2.0
64-bit
1996 230 4.5M 2
off-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8200 PA 2.0
64-bit
1997 300 4.5M 4
off-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8500 PA 2.0
64-bit
1998 440 140M 1.5
on-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8600 PA 2.0
64-bit
2000 550 140M 1.5
on-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8700 PA 2.0
64-bit
2001 875 186M 2.25
on-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8800
Mako
dual-core
PA 2.0
64-bit
2004 1000 300M 2×1.5
on-chip
32
off-chip
Itanium 2 2×4-way Yes Two cores, each:
4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8900
dual-core
PA 2.0
64-bit
2005 1100 317M 2×1.5
on-chip
64
off-chip
Itanium 2 2×4-way Yes Two cores, each:
4 Integer
4 Floating Point
2 Load/Store
MAX-2

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Third party CPUs

Some third parties have also developed their own PA-RISC chips.

Other PA-RISC processors overview
CPU ISA Release Clock
MHz
FETs Cache
L1/L2 KB
Bus Super
scalar
Units Controllers
on-chip
Hitachi
PA/50
PA 1.1
32-bit
1993 60 1.28M 12 ? 1-way? 1 Integer
1 Floating Point
Hitachi
HARP-1
PA 1.1
32-bit
1994 150 2.8M 24/1024 ? 2-way 2 Integer
1 Floating Point
(Vector)
Winbond W89K PA 1.1
32-bit
1994 33/66 1.1M 4 Intel 486 1-way 1 Integer none?
Winbond W90210
W90215
PA 1.1
32-bit
1997 33/66 ? 12 Intel 486 1-way 1 Integer
MAX-1
DRAM
DMA
PCI
I/O
Winbond W90220
W90221
PA 1.1
32-bit
1999 150 ? 8 Intel 486 1-way 1 Integer
1 MAC(DSP)
MAX-1
DRAM
DMA
PCI
IDE
I/O
VGA (W90221)
TV (W90221)
Oki OP32 PA 1.1
32-bit
1994 33 1.1M ? ? 1-way 1 Integer DRAM
DMA

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