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PA-RISC Processors

Introduction

The PA-RISC platform is based on RISC processors from HP and was used in HP computers from the 1980s until the early 2000s. Three major revisions of the PA-RISC architecture were developed:

  1. PA-RISC 1.0 (32-bit) implemented in several early processors and used in the very first PA-RISC servers; no MMU and no virtual memory.
    • Processors: NS-1, NS-2 and PCX. NS-2 tweaked the NS-1 design (both implemented in NMOS) and PCX implemented the NS-2 design on CMOS.
  2. PA-RISC 1.1 (32-bit), used in the PA-7x00 processors, and HP 9000 servers and workstations from the late-1980s and 1990s.
    • Processors: PA-7000 and PA-7100, the first PA-RISC 1.1 processors, and the later integrated lowcost PA-7100LC and PA-7300LC. The former two have VSC bus system interfaces, with the PA-7000 being an integrated successor to the earlier PCX and the PA-7100 adding superscalarity and an on-chip FPU. The two LC processors integrate additional processing logic, direct GSC system bus attachments and on-die memory controllers but have similar processor designs. The PA-7300LC extended the original PA-7100LC design with true on-chip cache and modified memory controller and bus interfaces.
  3. PA-RISC 2.0 (64-bit), which extended 32-bit PA-RISC 1.1 to 64-bit in the PA-8x00 processors and featured a redesign of most parts of the architecture, used in the late-1990s to 2000s in the last PA-RISC computers.
    • Processors: PA-8000 and PA-8200, the first PA-RISC 2.0 64-bit processors, were very similar. The subsequent 64-bit processors all were iterations of the basic PA-8000 core. PA-8500, PA-8600 and PA-8700 are direct evolutions of the PA-8000 with large on-chip caches. The PA-8600 and PA-8700 are slight modifications of the PA-8500 with different cache layouts and process technologies. PA-8800 and PA-8900 implemented dual PA-8700 cores onto single-dies with large off-die but on-chip caches.

Most HP Unix computers between the mid-1980s and early 2000s are based on PA-RISC — other HP product lines (as the HP 3000 systems) and some external integrators (OEMs) used PA-RISC processors as well.

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HP PA-RISC CPUs

The following PA-RISC processors have been developed and used by HP throughout the years. Some third parties have also developed their own PA-RISC chips.

HP PA-RISC processors overview
CPU ISA Released Clock
max
FETs L1 Cache
max
L2 Cache
max
Bus Super
scalar
SMP Units
TS-1 PA 1.0
32-bit
1986 8 MHz ? 128 KB I/D
off-chip
  Custom 1-way 1 Integer
External FPU
NS-1 PA 1.0
32-bit
1987 30 MHz 144k 128 KB
off-chip
  SMB 1-way 1 Integer
External FPU
NS-2 PA 1.0
32-bit
1989 27.5 MHz 183k 1 MB I/D
off-chip
  SMB 1-way Yes 1 Integer
External FPU
PCX PA 1.0
32-bit
1990 50 MHz 196k 1 MB I/D
off-chip
  SMB 1-way Yes 1 Integer
External FPU
PA-7000 PA 1.1a
32-bit
1991 66 MHz 577k 256 KB I
256 KB D
off-chip
  PBus/VSC 1-way 1 Integer
External FPU
PA-7100
PA-7150
PA 1.1b
32-bit
1992 125 MHz 850k 1 MB I
2 MB D
off-chip
PBus/VSC 2-way Yes 1 Integer
1 Floating Point
PA-7100LC PA 1.1c
32-bit
1994 100 MHz 900k 1 KB I
on-chip
2 MB
off-chip
GSC 2-way 2 Integer
1 Floating Point
MAX-1
PA-7200 PA 1.1d
32-bit
1995 140 MHz 1.3M 2 KB
on-chip
1 MB I
2 MB D
off-chip
Runway 2-way Yes 2 Integer
1 Floating Point
PA-7300LC PA 1.1e
32-bit
1996 180 MHz 9.2M 64 KB I
64 KB D
on-chip
8 MB
off-chip
GSC 2-way 2 Integer
1 Floating Point
MAX-1
PA-8000 PA 2.0
64-bit
1996 230 MHz 4.5M 1 MB I
1 MB D
off-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8200 PA 2.0
64-bit
1997 300 MHz 4.5M 2 MB I
2 MB D
off-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8500 PA 2.0
64-bit
1998 440 MHz 140M 512 KB I
1 MB D
on-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8600 PA 2.0
64-bit
2000 550 MHz 140M 512 KB I
1 MB D
on-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8700 PA 2.0
64-bit
2001 875 MHz 186M 768 KB I
1.5 MB D
on-chip
  Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8800
Mako
dual-core
PA 2.0
64-bit
2004 1 GHz 300M
768 KB I
768 KB D
on-chip
32 MB
off-chip
Itanium 2
4-way
Yes
4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8900
dual-core
PA 2.0
64-bit
2005 1.1 GHz 317M
768 KB I
768 KB D
on-chip
64 MB
off-chip
Itanium 2
4-way
Yes
4 Integer
4 Floating Point
2 Load/Store
MAX-2

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Third party CPUs

Other PA-RISC processors overview
CPU ISA Released Clock
max
FETs Cache Bus Super
scalar
Units Controllers
on-chip
Hitachi
PA/50
PA 1.1
32-bit
1993 60 MHz 1.28M L1 8/4 KB I/D ? 1-way? 1 Integer
1 Floating Point
Hitachi
HARP-1
PA 1.1
32-bit
1994 150 MHz 2.8M L1 8/16 KB I/D
L2 512/512 KB I/D
? 2-way 2 Integer
1 Floating Point
(Vector)
Winbond W89K PA 1.1
32-bit
1994 33/66 MHz 1.1M L1 2/2 KB I/D Intel 486 1-way 1 Integer none?
Winbond W90210
W90215
PA 1.1
32-bit
1997 33/66 MHz ? L1 4/8 KB I/D Intel 486 1-way 1 Integer
MAX-1
DRAM
DMA
PCI
I/O
Winbond W90220
W90221
PA 1.1
32-bit
1999 150 MHz ? L1 4/4 KB I/D Intel 486 1-way 1 Integer
1 MAC(DSP)
MAX-1
DRAM
DMA
PCI
IDE
I/O
VGA (W90221)
TV (W90221)
Oki OP32 PA 1.1
32-bit
1994 33 MHz 1.1M ? ? 1-way 1 Integer DRAM
DMA