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PA-RISC Processors

Introduction

The PA-RISC platform is based on RISC processors from HP and was used in HP computers from the 1980s until the early 2000s. Three major revisions of the PA-RISC architecture were developed:

  1. PA-RISC 1.0 (32-bit) implemented in several early processors and used in the very first PA-RISC servers; no MMU and no virtual memory
  2. PA-RISC 1.1 (32-bit), used in the PA-7x00 processors, and HP 9000 servers and workstations from the late-1980s and 1990s
  3. PA-RISC 2.0 (64-bit), which extended 32-bit PA-RISC 1.1 to 64-bit in the PA-8x00 processors and featured a redesign of most parts of the architecture, used in the late-1990s to 2000s in the last PA-RISC computers.

Most HP Unix computers between the mid-1980s and early 2000s are based on PA-RISC — other HP product lines (as the HP 3000 systems) and some external integrators (OEMs) used PA-RISC processors as well.

Overview table

PA-RISC processors overview
CPU ISA Clock
max		 FETs L1 Cache
max		 L2 Cache
max		 Bus Super
scalar		 SMP Units
TS-1 PA 1.0
32-bit		 8 MHz ? 128 KB I/D
off-chip		   Custom 1-way No 1 Integer
External FPU
NS-1 PA 1.0
32-bit		 30 MHz 144k 128 KB
off-chip		   SMB 1-way No 1 Integer
External FPU
NS-2 PA 1.0
32-bit		 27.5 MHz 183k 1 MB I/D
off-chip		   SMB 1-way Yes 1 Integer
External FPU
PCX PA 1.0
32-bit		 50 MHz 196k 1 MB I/D
off-chip		   SMB 1-way Yes 1 Integer
External FPU
PA-7000 PA 1.1a
32-bit		 66 MHz 577k 256 KB I
256 KB D
off-chip		   PBus/VSC 1-way No 1 Integer
External FPU
PA-7100
PA-7150		 PA 1.1b
32-bit		 125 MHz 850k 1 MB I
2 MB D
off-chip		 PBus/VSC 2-way Yes 1 Integer
1 Floating Point
PA-7100LC PA 1.1c
32-bit		 100 MHz 900k 1 KB I
on-chip		 2 MB
off-chip		 GSC 2-way No 2 Integer
1 Floating Point
MAX-1
PA-7200 PA 1.1d
32-bit		 140 MHz 1.3M 2 KB
on-chip		 1 MB I
2 MB D
off-chip		 Runway 2-way Yes 2 Integer
1 Floating Point
PA-7300LC PA 1.1e
32-bit		 180 MHz 9.2M 64 KB I
64 KB D
on-chip		 8 MB
off-chip		 GSC 2-way No 2 Integer
1 Floating Point
MAX-1
PA-8000 PA 2.0
64-bit		 230 MHz 4.5M 1 MB I
1 MB D
off-chip		   Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8200 PA 2.0
64-bit		 300 MHz 4.5M 2 MB I
2 MB D
off-chip		   Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8500 PA 2.0
64-bit		 440 MHz 140M 512 KB I
1 MB D
on-chip		   Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8600 PA 2.0
64-bit		 550 MHz 140M 512 KB I
1 MB D
on-chip		   Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8700 PA 2.0
64-bit		 875 MHz 186M 768 KB I
1.5 MB D
on-chip		   Runway 4-way Yes 4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8800
2-core		 PA 2.0
64-bit		 1 GHz 300M 2×
768 KB I
768 KB D
on-chip		 32 MB
off-chip		 Itanium 2 2×
4-way		 Yes 2×
4 Integer
4 Floating Point
2 Load/Store
MAX-2
PA-8900
2-core		 PA 2.0
64-bit		 1.1 GHz 317M 2×
768 KB I
768 KB D
on-chip		 64 MB
off-chip		 Itanium 2 2×
4-way		 Yes 2×
4 Integer
4 Floating Point
2 Load/Store
MAX-2
Hitachi
PA/50		 PA 1.1
32-bit		 60 MHz 1.28M 8 KB I
4 KB D
on-chip		   ? 1-way? No? 1 Integer
1 Floating Point
Hitachi
HARP-1		 PA 1.1
32-bit		 150 MHz 2.8M 8 KB I
16 KB D
on-chip		 512 KB I
512 KB D
off-chip		 ? 2-way No? 2 Integer
1 Floating Point
(Vector)

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