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Convex Exemplar SPP1000, SPP1200 & SPP1600

Quick Facts
Introduced 1994-1996
CPU 2-16 (CD)/2-8 (XA)
PA-7100/
PA-7200
100-120 MHz
Caches 512 KB-2 MB L1
RAM 4 GB (CD)
2 GB (XA)
Design Crossbar
Drives 20 SCSI
Expansion 16 SBus (CD)
8 SBus (XA)
Bandwidth CPU/Mem 1 GB/s
I/O 250 MB/s
XBAR 1.25 GB/s
SCI 2.4 GB/s
I/O SCSI
Console
SCI/CTI links (XA)

Overview

The Convex Exemplar SPP1x00 are scalable 32-bit mainframe/technical computing systems, with either PA-7100 (SPP1000) or PA-7200 (SPP1200 and SPP1600) processors. Previous Convex designs used custom Convex processors, with the SPP line Convex switched to third-party processors with the HP PA-RISC. This probably colluded witht the close collaboration between Convex and HP starting in the early 1990s, which resulted in the join HP/Convex marketed Exemplar SPP2000 (the direct 64-bit successor of the SPP1x00s with a slightly modified architecture) and the takeover of Convex by HP in 1994, which resulted in the HP-branded V-Class servers (the 64-bit non-clusterable HP 9000/V2200 and V2250 and the up to four-way clusterable HP 9000/V2500 and V2600).

The 32-bit Convex SPP1x00 systems consist of three distinct system building concepts, the CD compact systems, the XA eXtended Architecture hypernodes and the XA clusters:

The internal Exemplar architecture is based on a 5x5 crossbar with the central internal switching component (the crossbar) connecting the resources to each other by forming matrix connections between the devices’ input and output ports (5x5 because the crossbar has five ports for processors, memory and I/O).

The Nodes and Clusters are controlled and booted via a seperate workstation connected to it, frequently a IBM RS/6000 computer running AIX, which faced the Exemplar’s console and control I/O (in the case of a cluster only one node had a control workstation). Also apparently used were HP 9000/715 workstations running as teststation.

Internals

CPU

It is not quite clear how the CD models relate to the XA models — the XA clusters consist of several 2-8 processor hypernodes while the CD models were shipped with up to 16 processors. Either the CDs are different machines than the XA hypernodes or they are simply two XA hypernodes coupled together, without any additional SCI/CTI expansion possibilities.

Chipset

The chipset is based completely on an own Convex design and centers around the Convex five-port crossbar, later improved on the SPP2000 with eight ports and used in HP’s V-Class.

  1. 5x5 nonblocking crossbar, with five crossbar ports, is the central part of the system, it connects to four functional units (memory, SCI links and processor) and with the fifth port to the local system I/O. The four functional units contain each a memory controller, SCI controller and an agent for two processors. Memory and processor use different data links to the crossbar — memory access always goes over the crossbar, even from a processor to the memory in the same functional unit. Each crossbar port has a data rate of 250 MB/s, giving the crossbar a combined peak bandwidth of 1.25 GB/s. The crossbar is implemented in Gallium arsenide gate arrays (GaAs, 250K transistors), quite a rarity, since it was very expensive and difficult to handle.
  2. Four CPU Agents attach to the crossbar and provide access for the processors to the memory via the crossbar over a 250 MB/s crossbar port shared with the memory controller (see below).
  3. Four Convex Coherent Memory Controllers (CCMCs) attach each one four-way interleaved memory board to the crossbar. The CCMCs additionally do cache coherency and interface to the Convex’s SCI (CTI) link for inter-hypernode connection. [It is not quite clear if the CCMCs share the whole 250 MB/s port/data connections with the CPU agents on the same functional unit, or if CCMC and CPU agent attach to separate lines of the crossbar port —Ed.] The CTI interface — or the complete CCMC — were apparently also GaA chips.
  4. Exemplar I/O (Input/Ouput) Subsystem connects to the fifth 250 MB/s crossbar port and attaches the I/O subsystem controllers to the crossbar and this memory and processors.

» View a system-level ASCII illustration of the crossbar architecture.

Buses

Memory

Expansion

Drives

Clustering

Multiple SPP1x00/XA systems can be connected together to form a single large system.

External connectors

References

Manuals

Articles

Other

Operating systems

Benchmarks

Model SPEC92
fp
SPEC95
int
SPEC95
fp
SPEC95
rate, int
SPEC95
rate, fp
SPP1000 3.27 3.98
SPP1200 185
SPP1600 8-CPU: 290
16-CPU: 541
32-CPU: 996
8-CPU: 383
16-CPU: 744
32-CPU: 1444

Compare these with other results on the Benchmarks page.

Physical dimensions

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