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HP V2500 & V2600

Quick Facts
Introduced 1999-2000
CPU 2-32 PA-8500 (V2500)
2-32 PA-8600 (V2600)
440-552 MHz
Caches 1.5 MB L1
RAM 32 GB
Design HyperPlane
Drives 16 SCSI
Expansion 28 PCI
Bandwidth CPU 7.5 GB/s
Mem 15 GB/s
I/O 1.9 GB/s
XBAR 15.3 GB/s
SCI 3.8 GB/s
I/O SCSI
Console
SCI (CTI/SCA) links

Overview

The V2500 and V2600 are second generation scalable PA-RISC V-Class servers based on the Convex Exemplar architecture. They can hold up to 32 64-bit PA-RISC processors in a single cabinet. As their Convex SPP2000 predecessors, and contrary to their V2200/V2250 cousins, multiple systems (up to four) can be interconnected via CTI links. The resulting combined system can have up to 128 CPUs and appears to the operating system as a single computer. Architecturally the interconnected V2500s/V2500s are ccNUMA computers, cache-coherent Non-Uniform Memory Access.

The V-Class servers are based on a crossbar architecture — one central internal switching component links the various computing resources to each other by forming matrix connections. The V2500 and V2600 use HP’s own HyperPlane crossbar chipset, consisting of four central crossbar ASICs and various other chipset components to attach memory, processors and I/O.

The architecture is a direct continuation from the Convex Exemplar — the HP/Convex SPP1x00 and SPP2000 S-Class and X-Class use a similar crossbar-based system design (based on GaA chips) which was upgraded for the V-Class with faster processors and memory. A multi-node V2500/V2600 system architecture (SCA) does not conform fully to the PA-RISC 2.0 reference architecture — the firmware layer emulates a reference-compliant PA-RISC system for the operating system, a standard HP-UX 11. However several changes had to be made to the HP-UX kernel to accomodate the V-Class’s special architecture (also called technical anomalies; cf. the HP Scalable Computing Architecture paper in the References).

The V2500s and V2600s are controlled via a teststation (also called SSP, Service Support Processor), a separate workstation that runs its own operating system and controls and monitors the V-Class server (either a HP 9000/712 or B180L workstation with two Ethernet interfaces running HP-UX 10.20; earlier Convex systems apparently used IBM RS/6000 workstations running AIX to control the Exemplar systems). The SSP/teststation connects to the Core Utilities Board (CUB), which provides booting, system monitoring and diagnostics, and console connections (connected via one LAN and one special serial link).

Internals

CPU

Chipset

The V-Class V2500 and V2600 are based on the HP HyperPlane crossbar which connects the CPU and I/O to the system main memory.

  1. HyperPlane crossbar, 8x8, non-blocking, consists of four Routing Attachment controllers (RACs) and is the central part of the system, it connects the memory to the processor buses and I/O channels. There are eight ports for agents for CPUs and I/O — each agent connects to two or four CPUs and one I/O channel —, and eight ports for memory. Each crossbar port has a path width of 64-bit, giving it 960 MB/s peak bandwidth. The peak bandwidth of the HyperPlane crossbar/RACs is 15.3 GB/s combined.
  2. Eight Processor Agent controllers (PACs) (also SPAC) attach to the crossbar and provide access for the processors (Runway buses) and I/O controllers (I/O channels) to the memory via the crossbar over a 1.9 GB/s datapath (four 32-bit, unidirectional buses from two ports on the PAC connect to two Hyperplane crossbar RACs; each PAC thus communicates with only two of the system’s four RACs). The I/O channels on the agent have a maximum bandwidth of 240 MB/s. Each PAC has two Runway processors buses (64-bit, bidirectional) which have an aggregate peak bandwidth of 960 MB/s.
  3. Eight PCI-bus Interface controller (SAGA) connect the 240 MB/s I/O channels/PCI buses to the PACs.
  4. Eight Memory Access controllers (MACs) (also SMAC) attach each one 32-way interleaved memory board to the Hyperplane crossbar. Each MAC has a bandwidth of 1.9 GB/s (four 32-bit, unidirectional buses from two ports on the MAC connect to two Hyperplane crossbar RACs)
  5. The Core Utilities board (CUB) provides interrupts and the central system logic, it connects to the Midplane Interconnect Board (MIB). The Core Logic Bus from the CUB attaches to the devices on the PACs.
  6. Eight Toroidal Access Controller (STACs) connect to a variation of the Scalable Coherent Interconnect (SCI) to one or two rings. The combination of STACs and these (SCI) rings is referred to as Coherent Toroidal Interconnect (CTI).

» View a system-level ASCII illustration of the crossbar architecture.

The remainder of the system I/O consist of standard HP PCI controllers, frequently shipped in default configuration with one of the following:

Buses

Memory

Expansion

Drives

Clustering

Multiple V-Classes can be connected together to form a single large system resulting in a SCA (Scalable Computing Architecture) system:

External connectors

References

Manuals

Articles

Operating systems

Benchmarks

Model SPEC95
rate, int
V2500 16-CPU: 4002
32-CPU: 7481
V2600 16-CPU: 5164
32-CPU: 9315

Compare these with other results on the Benchmarks page.

Physical dimensions

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