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HP/Convex SPP2000 (S-Class/X-Class)

Quick Facts
Introduced 1997
CPU 4-16 PA-8000
180 MHz
Caches 1/1 MB L1
RAM 16 GB
Design Crossbar
Drives 20 SCSI
Expansion 28 PCI
Bandwidth CPU 7.5 GB/s
Mem 15 GB/s
I/O 1.9 GB/s
XBAR 15.3 GB/s
SCI 3.8 GB/s
I/O SCSI
Console
SCI (CTI)

Overview

The HP/Convex Exemplar SPP2000 are large scalable PA-RISC computing servers and the direct predecessors of the later HP V-Class (V2200, V2500 et al). Originally developed by Convex, the SPP2000 are based on a crossbar architecture with the central internal switching component connecting the resources to each other by forming matrix connections between the devices’ input and output ports.

A single SPP2000 computer can hold up to sixteen 64-bit PA-8000 processors with 16 GB of memory in a single Node — called S-Class. The SPP2000 can form a large-scale system by connecting single Nodes with SCI links into a larger cluster of up to 32 nodes/512 processors. The resulting interconnected system are called X-Class, and are are ccNUMA computers. The clustering capabilities of their successors, the V2500, have been reduced significantly — in contrast to the 32-node maximum of SPP2000 clusters, V2500s only can be clustered to groups of four.

As the other Exemplar systems, the SPP2000/S-Class are operated and controlled via so-called teststations, Unix workstations that connect to a central management board in the single nodes which provides booting, system monitoring and diagnostics, and console connections. These teststations were either IBM RS/6000 AIX systems or later, more common, HP 9000 workstation running HP-UX.

Internals

CPU

Chipset

The SPP2000 is based on the Exemplar crossbar architecture which connects the CPU and I/O to the system main memory.

  1. 8x8 nonblocking crossbar is the central part of the system, it connects the memory to the processor buses and I/O channels. There are eight ports for agents for CPUs and I/O — each agent connects to two CPUs and one I/O channel —, and eight ports for memory. Each crossbar port has a path width of 64-bit, giving it 960 MB/s peak bandwidth. The peak bandwidth of the crossbar is 15.3 GB/s combined. The crossbar in the original SPP1x00 Exemplar design was built with GaA chips, the SPP2000 in standard CMOS with 1.1M transistors.
  2. Eight Data Mover/Agents attach to the crossbar and provide access for the processors with Runway buses and I/O controllers to the memory via the crossbar over a 1.9 GB/s datapath with four 32-bit, unidirectional buses from two ports on the Agent connect to two crossbar ports. The I/O channels on the agent have a maximum bandwidth of 240 MB/s. Each Agent has two Runway processors buses with an aggregate bandwidth of 960 MB/s.
  3. Eight PCI controller connect the 240 MB/s I/O channels/PCI buses to the Agents.
  4. Eight Memory controllers attach each one four-way interleaved memory board to the Hyperplane crossbar. Each Memory controller has a bandwidth of 1.9 GB/s. The memory controllers probably also interface with the CTI interconnection.

» View a system-level ASCII illustration of the crossbar architecture.

Buses

Memory

Expansion

Drives

Clustering

Multiple Exemplar SPP2000/HP S-Class systems can be connected together to form a single large system, a Wall/X-Class.

External connectors

References

Articles

Operating systems

Benchmarks

Model SPEC95
int
SPEC95
fp
SPEC95
rate, int
SPEC95
rate, fp
SPP2000/S-Class/X-Class 11.8 18.7 92.5
2-CPU: 183
4-CPU: 363
6-CPU: 539
8-CPU: 713
10-CPU: 867
12-CPU: 1012
16-CPU: 1307
141
2-CPU: 276
4-CPU: 524
6-CPU: 739
8-CPU: 935
10-CPU: 1085
12-CPU: 1220
16-CPU: 1413

Compare these with other results on the Benchmarks page.

Physical dimensions

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