PA-RISC information - since 1999

PA-RISC Buses

Overview

Many different buses and bus systems were used in PA-RISC computers. Some were custom HP designs, especially the system main buses and early I/O buses such as VSC and GSC. For I/O devices HP used some custom designs as well but made use of industry buses such as EISA, PCI and others soon.

Buses used in PA-RISC computers overview
Type Frequency
max		 Width Data rate
max		 Usage
System buses
GSC 40 MHz 32-bit 160 MB/s System bus and I/O
HSC/GSC+ 40 MHz 32-bit 160 MB/s System bus and I/O
GSC-2 40 MHz? 32-bit 256 MB/s System bus and I/O
VSC 60 MHz 32-bit
64-bit 		240 MB/s
480 MB/s		 System bus
SMB 30 MHz 64-bit ? System bus
CPU buses
PBus 66 MHz? 64-bit ? CPU
Runway 120 MHz 64-bit 960 MB/s CPU
Runway+ 125 MHz 64-bit ~2 GB/s CPU
Device and I/O buses
EISA 8.3 MHz 32-bit 33 MB/s I/O bus
SGC 25 MHz? 32-bit 100 MB/s I/O bus
HP-PB 8 MHz 32-bit 32 MB/s I/O bus
PCI-32 66 MHz 32-bit 266 MB/s I/O bus
PCI-64 66 MHz 64-bit 533 MB/s I/O bus
PCI-X 133 MHz 64-bit 1066 MB/s I/O bus

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GSC

The General System Connect GSC bus is the primary system and I/O bus on most of second-generation 32-bit HP 9000 workstations. GSC connects most of the I/O devices to the central system bus and chipset, with some CPUs attaching directly to it like the PA-7100LC and PA-7300LC HSC is a variant of GSC.

Expansion cards form factors

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VSC

Viper System Connect (VSC) is the central system bus of computers with PA-7000 and PA-7100 PA-RISC processors. It connects the HP Viper central bus controller, also known as MIOC, PMI or PIC, to the memory and I/O buses. In multiprocessor configurations, each processor has its own Viper controller, which connects to a shared VSC bus with attachments to all Viper controllers, memory and I/O converters.

VSC is sometimes called SGC, the extension of VSC to graphics cards.

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System Main Bus (SMB)

In early 1980s PA-RISC 1.0 systems, NS-1, NS-2 and PCX processors attach to the System Main Bus (SMB) via bus converters.

TS-1, the first PA-RISC processor used a simpler version of this setup and directly attached the CPU to the Central Bus CTB with 32-bit at 8 MHz. Here, all the CPU, memory and I/O devices directly connect to the CTB.

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PBus

Systems with PA-7000 or PA-7100/PA-7150 processors use the PBus processor bus between the CPU and external memory controller Viper. These systems with VSC main bus mostly use ASP chipsets for system I/O and devices. On multi-processor systems with a PA-7100 two attachment variants are possible — either shared memory controller on two processors or shared system bus with up to eight processors.

CPU attachment

  1. PBus is the main processor and memory bus
    • CPU attaches to PBus with 32-bit, with ECC 40-bit
  2. Viper, the main memory and I/O controller attaches to PBus
    • Memory attaches to MIOC via 64-bit, with ECC 72-bit
  3. VSC, the system main bus, attaches to MIOC and various I/O controllers
    • Attaches via 32-bit on PA-7000 or 64-bit on PA-7100 at MIOC
  4. I/O adapters attach to VSC

View a system-level illustration (ASCII) for single-processor.

Multiprocessor attachment

  1. Two-way SMP Low Cost: Two CPUs share a PBus and attach to the same MIOC. Memory attaches directly to MIOC, I/O attaches via VSC to MIOC.
  2. Scalable MP: Each CPU has its own MIOC. All MIOCs in the system share a VSC bus, to which I/O and memory attach.

View a system-level illustration (ASCII) on PA-7100 multi-processor.

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Runway

Runway is the system bus of newer 64-bit systems with PA-7200 and PA-8000 processors and up. It is a synchronous, split-transaction bus. PA-8500, PA-8600 and PA-8700 use an advanced version of Runway, Runway+/Runway DDR.

CPU attachment

Systems with PA-7200, PA-8000 and PA-8200 processors use Runway and split I/O and memory controllers —with frontends and backends to interface the CPU and its processor bus to customized bus attachments. This allowed HP to use the frontend parts of these chipsets with a variety of different system design which only required modified backend parts for new memory or I/O technologies.

  1. Runway is the main processor and memory bus for one to four processors, 64-bit, parity-protected
  2. MMC is the master memory controller which attaches to Runway with 64-bit (at 120 MHz at a data rate of 960 MB/s). Memory attaches to MMC via slave memory controllers (SMC) at 128-bit 60 MHz data ECC and 39-bit 60 MHz address buses
  3. U2/UTurn I/O adapters attach the main I/O bus and system to the Runway processor bus with 64-bit. Two I/O adapters (IOAs) per U2/UTurn chip with data rate depends on Runway clock with 120 MHz and 64-bit: 960 MB/s
  4. GSC+, the main system bus, attaches to the U2/UTurn IOAs via 32-bit at a fraction of Runway/IOA clock, mostly 40 MHz.
  5. I/O adapters and slots attach to GSC+, like LASI chipset, video adapters, I/O slots and bus adapters, including EISA, VME and PCI

Runway+ DDR CPU attachments

PA-RISC 64-bit processors PA-8500, PA-8600, PA-8700 use a Runway bus with increased data rate and different I/O and memory controllers, often Astro chipset.

  1. Runway+/Runway DDR is the main processor and memory bus for one to four processors, 64-bit, parity-protected
  2. Astro is the main memory and I/O controller which attaches to Runway
    • Attaches to Runway+/Runway DDR with 64-bit at 125 MHz with 2.0 GB/s
    • Memory attaches to Astro with a peak data rate of 2.0 GB/s at 125 MHz
    • Up to eight I/O links or ropes with each 250 MB/s attach to Astro
  3. Elroy I/O adapters attach PCI bridges via I/O ropes to Astro
  4. PCI, the main I/O buses, attach to the multiple Elroy bridges
  5. I/O devices, adapters and slots attach to PCI

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EISA

Extended ISA or EISA is an device I/O and expansion bus that replaced the 1980s ISA bus in HP Unix workstations and servers. EISA buses are found in various early 32-bit workstations, either on-board or through a bus converter; this industry standard bus made it possible to use third-party, generic expansion cards such as network interfaces and SCSI controllers.

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SGC

System Graphics Connect (SGC) is the extension of the main VSC system bus in early 32-bit HP 9000 700 workstations. Expansion cards are available in two different form factors: EISA and DIO.

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HP-PB

The HP-Precision Bus HP-PB, sometimes HP/PB, is the I/O bus in many older 32-bit HP servers. Two form factors/sizes of HP-PB expansion cards were sold: single and double.

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PCI

With PCI HP changed its HP 9000 workstation and server design to an industry standard expansion and device bus. This allowed for using more off-the-shelf I/O chips and cards. Some HP PCI expansion cards for HP 9000 computers are relabeled third-party or OEM designs with PA-RISC compatible firmware and HP-UX driver.

Proper HP-UX drivers are the limiting factor for generic third-party PCI expansion cards in PA-RISC systems. In most cases drivers are only available for the HP-branded products. Open source operating systems as Linux or OpenBSD support many more devices in their PA-RISC ports.

PCI buses used in PA-RISC computers overview
PCI Clock Width Data rate
max		 Signalling
PCI-32/33 33 MHz 32-bit 133 MB/s 3.3 V/5 V
PCI-32/66 66 MHz 32-bit 266 MB/s 3.3 V
PCI-64/33 33 MHz 64-bit 266 MB/s 3.3 V/5 V
PCI-64/66 66 MHz 64-bit 533 MB/s 3.3 V
PCI-X 64/66 66 MHz 64-bit 533 MB/s 3.3 V
PCI-X 64/100 100 MHz 64-bit 800 MB/s 3.3 V
PCI-X 64/133 133 MHz 64-bit 1066 MB/s 3.3 V

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Documentation