PA-RISC Chipsets
Overview
Most HP PA-RISC computers used proprietary HP chipsets and system designs. Early 32-bit workstations (HP 9000/700) and servers (HP 9000/800) from the 1990s used different chipsets. Later on, the system platforms of workstations and servers moved closer and used the same chipsets.
| Architecture and CPUs | Chips | Usage |
|---|---|---|
| Early designs | SIU/SPI | CPU bridge |
| TS-1, NS-1, NS-2, PCX | CTB | I/O bridge |
| ASP/Viper | Viper | Memory and I/O controller |
| PA-7000, PA-7100 | ASP | I/O chipset |
| LASI | MIOC | Memory and I/O controller |
| PA-7100LC, PA-7300LC | LASI | I/O chipset |
| Wax | EISA bridge | |
| Dino | PCI bridge | |
| Cujo | PCI-64 bridge | |
| U2/UTurn | MMC/SMC | Memory controller |
| PA-7200, PA-8000, PA-8200 | U2 or UTurn | I/O controller |
| LASI | I/O chipset | |
| Wax | EISA bridge | |
| Dino | PCI bridge | |
| Cujo | PCI-64 bridge | |
| Astro | Astro | Memory and I/O controller |
| PA-8500, PA-8600, PA-8700 | Elroy | Bus bridge to I/O |
| Stretch | DEW | CPU bridge |
| PA-8500, PA-8600, PA-8700 | Prelude | Memory controller |
| IKE | I/O controller | |
| Elroy | PCI-64 bridge | |
| Cell | CC | Memory and I/O controller |
| PA-8700, PA-8800, PA-8900 | XBC | Crossbar |
| SBA | I/O controller | |
| Elroy | PCI-64 bridge | |
| zx1 | Pluto | I/O and memory controller |
| PA-8800, PA-8900 | Mercury | PCI, PCI-X, AGP bridge |
Chipsets were tied to specific architectures but sometimes used in different generations of computers or implementations.
Early designs: Early 32-bit PA-RISC systems of the late 1980s used custom designs based on the SIU/SPI main bus interfaces and the SMB bus. The computing and I/O units consisted of a large number of individual chips and used CIO and HP-PB I/O buses.
ASP/Viper: Computers with 32-bit PA-7000 and PA-7100 processors mostly used the ASP chipset and Viper memory controller, with VSC CPU, GSC system and SGC and EISA expansion buses.
LASI: Developed as highly-integrated chipset and system design, many LC low-cost systems with PA-7100LC and PA-7300 LC processors used LASI and GSC as system and I/O bus.
U2/UTurn: PA-RISC computers based on 32-bit and 64-bit processors with a Runway processor interface used a U2 or UTurn system design that attached GSC- and PCI-based I/O and memory via adapters to the Runway bus.
Astro: Some PA-8500, PA-8600 and PA-8700 systems use a rope-based architecture with Astro as main system controller and Runway+ buses with I/O devices controlled by Elroy PCI bridges.
Stretch: Stretch was a 64-bit system design for midrange servers based on PA-8500 to 8700 processors, with a central system controller and links to processor and I/O controllers and PCI bridges. The main system bus is Itanium with converters for the PA-RISC processor Runway bus.
Cell: This was a crossbar chipset used in few HP 9000 Integrity servers and some Superdome models.
The main design feature were individual system or processor cells
that were interconnected by a CEC component and central crossbars.
zx1: The zx1 chipset was a HP Itanium chipset bus used in later HP 9000 and Integrity PA-RISC servers as well. It consists of two purpose-built main parts that connect the processor, memory and I/O to the Itanium system main buses: Pluto and Mercury.