HP FOCUS Processor
HP FOCUS was the architecture of the HP 9000 500 – the first HP 9000 series –, a 32-bit HP custom design that predated widespread RISC usage and the PA-RISC architecture. FOCUS was a stack architecture implemented in five NMOS-III VLSI chips fabbed in 1.5 micron: the CPU chip, I/O processor (IOP), memory controller, 128Kb RAM (16 KB cache) and clock driver.
FOCUS processors ran at 18 MHz and had a
direct address range of
500 MB (probably 29-bit direct addressing for
512 MB). It was fabricated with 450,000 FETs, integrated with three Floating-Point chips onto one
finstrate CPU board.
The FOCUS CPU was microcoded with 9,000 38-bit microcode control stores and implemented the HP 3000 computers’ stack-based architecture in 32-bit.
All internal data paths and registers are 32-bit wide.
Due to heat dissipation difficulties the ICs were mounted on special printed-circuit boards called
finstrates — the board has
a 1mm copper sheet as core to which the IC substrate is epoxied directly.
The I/O Processor (IOP) executes all I/O instructions and handles the transactions from/to the eight attached HP CIO channels. It has an I/O bandwith of 5.1 MB/s burst and 973 KB/s multiplexed. The IOP was also a microprogrammed (4,608 32-bit microcode stores) NMOS-III VLSI chip.
At least one IOP to interface with the I/O buses was needed so up to six CPUs were supported in hardware but only three in software. Up to two additional IOPs could be installed for more I/O options; each additional IOP needed an I/O expander which provided the I/O channels extension, the CIO bus.
The three finstrates boards of CPU, IOP and 256 KB RAM were installed in a 12-slot HP 9000/520 module. This allowed configurations of up to 10 MB of RAM; memory cards could be substituted to construct multiprocessor systems. The CPU, IOP and memory controller communicated via the memory processor bus MPB. The 44-line, 18 MHz, 36 MB/s MPB supports up to seven (other sources mention three/three) CPUs or IOPs and fifteen memory controllers.
The FOCUS is a stack architecture, with 230 instructions (both 32 bits and 16 bits wide), a segmented memory model, and no general purpose programmer-visible registers. There are thirty-nine 32-bit registers in the CPU hardware — thirty-one internal 32-bit general purpose registers, two 32-bit ALU registers, and others.
It has a flat address space but that is not really what most programs see: their access to memory is largely described by registers that contain the absolute memory addresses of segment boundaries. For example, instructions come from the current code segment, which is described by three registers: P, the program counter, which is a 32-bit register containing the absolute address of the instruction being executed; PB, the program base register, which is a 32-bit register containing the absolute address of the first word of the current code segment; and PL, the program limit register, which is a 32-bit register containing the absolute address of the last word of the current code segment.
The data segment also has base (DB) and limit (DL) registers, and so does the stack segment (SB, SL). The stack segment also has a stack pointer (S) and a stack marker pointer (Q) which points to the current procedure’s activation record on the stack.
There is also an index register, a status register, a flags register (really a sort of debugging-state register), a message register (interrupting conditions) and message mask register (which enables/disables interrupts from the message register), a breakpoint register, and a couple of registers which are for the memory controllers to talk to the CPU.
The machine instruction set is oriented toward moving words between memory and the top of the stack, and operating on the words at the top of the stack. To take an addition of two numbers: load one, load the other, execute an ADD instruction, and then a store instruction if the result should be kept somewhere in memory other than on the stack.
The stack is in memory, there are (probably) some numbers of
top of stack registers inside the processor to keep things moving
relatively quickly, but these registers are not otherwise visible
to the programmer.
- FOCUS stack architecture, 32-bit
- CPU consists of five VLSI chips
- Clock speed 18 MHz
- External Floating Point Unit
- I/O Processor (IOP)
- Computing units:
- Integer/load/store unit
- Floating point
- Thirty-one 32-bit integer registers, two ALU registers, plus external floating point registers
- Cache L1 16 KB instruction and data off-chip
- Up to six processors (SMP) supported in hardware, three in software (OS)
- Up to
500MB main memory could be addressed in a single system (10 MB in reality)
- CPU attaches via MPB bus to memory, I/O, 44-bit bus, 36 Mb/s data rate
- One circuit board, CPU implemented in NMOS-III, five chips 1.5µ
- HP 9000 500: 520, 530, 540, 550
- An 18- MHz, 32-bit VLSI Microprocessor (.pdf, pp. 7-10) Kevin P. Burkhart (August 1983. Hewlett Packard Journal. Accessed 15 January 2008 at hpmuseum.net)
- Hewlett-Packard 9000 Series 520 Frank McConnell (1997. Accessed January 2008)
Pictures © Hewlett Packard, scans from product brochures, from hpmuseum.net and 1000bit.it