OpenPA.net

PA-RISC Hardware

Overview

The computers covered by this site are based on HP PA-RISC architecture and processors from the 1980s to 2000s. Most of the chipsets and system designs used were custom HP for its PA-RISC servers and workstations and connected to I/O devices by HP and industry-standard buses. Storage was usually based on SCSI and implemented with SCSI controllers from third-parties, with the graphics using custom HP video adapters and the rest of I/O using industry components.

Hardware periods

Hardware components and system designs used in PA-RISC computers by HP can be divided roughly in four phases in the PA-RISC history from the 1980s to the mid-2000s.

PA-RISC hardware period table
Period Processors Design Chips
I Infancy: Early Architecture
TS-1, NS-1, NS-2, PCX Early SIU/SPI, CTB
II Growth: 32-bit 1990s
PA-7000, PA-7100 ASP/Viper Viper. ASP
III Maturity: The heydays
PA-7100LC, PA-7300LC LASI MIOC, LASI, Wax, Dino
PA-7200, PA-8000, PA-8200 U2/UTurn MMC/SMC, U2, UTurn,
LASI, Wax, Dino, Cujo
PA-8500, PA-8600, PA-8700 Astro Astro, Elroy
Stretch DEW, Prelude, IKE, Elroy
IV Decline: 64-bit to Itanium
PA-8700, PA-8800 PA-8900 Cell CC, XBC, SBA, Elroy
PA-8800 PA-8900, Itanium 2 zx1 Pluto, Mercury

I. Infancy: Early Precision Architecture of the late 80s. First versions of PA-RISC were released in the late 1980s as Precision Architecture with early implementations of processors and chipsets for the early HP 9000 800 series of computers. A few systems were released, but details on their exact architecture remain fuzzy. These designs were quickly superseded by new designs for both servers and workstations in the 1990s.

Systems sold in that period used PA-RISC processors such as TS-1, NS-1, NS-2 and PCX and were based on custom HP system designs. Chipsets used were the SIU/SPI main bus interfaces that connected the processors to the SMB bus that links it to memory, I/O and devices. In most cases the system processing and I/O units are made up of a large number of individual chips or boards forming the central chipset with the CIO and HP-PB I/O buses.

II. Growth: 32-bit PA-RISC in the early 1990s. PA-RISC workstations and servers became popular with PA version 1.1 processors and new chipsets and system designs built on it.

Major innovations and developments took place from the late 1980s to the early 1990s to produce the PA-RISC 1.1 architecture and popular Unix systems based on it from the early 1990s on. They did not have much in common with the early PA-RISC 1.0 systems.

Along with the architecture, PA-RISC hardware designs matured throughout the early 1990s, with popular 32-bit PA-7000 and PA-7100 systems using the ASP chipset and Viper memory controller. They utilize the VSC CPU/memory, GSC system main and SGC and EISA expansion buses, with servers using HP-PB I/O buses, all provided by separate I/O adapters/bus bridges.

III. Maturity: The PA-RISC heydays in the 1990s. Many innovations and improvements took place in the heydays of PA-RISC in the 1990s, with 32-bit low-cost LC processors, a shift to 64-bit PA-RISC 2.0 and quite advanced designs and I/O components.

From the mid-1990s on, the integrated, low-cost PA-7100LC and PA-7300LC systems use the highly integrated LASI chipset, which combines most functions and I/O on a single chip, and an on-CPU MIOC memory controller. These system use GSC or GSC+ as main bus and a variety of expansion buses via bus adapters, ranging from HSC/GSC, EISA to PCI and VME. EISA is provided by Wax, PCI by Dino.

PA-7200 and 64-bit PA-8000 and some PA-8200 systems use the U2/Uturn I/O adapters, which attach two GSC/HSC buses to the main Runway bus, and MMC/SMC memory controllers. I/O is realized on the GSC bus with the LASI chipset and Wax and Dino I/O adapters.

PA-RISC computers from the turn of the century used 64-bit PA-8500, PA8600 and PA-8700 designs with a rope-based architecture with Astro as main system controller and separate Runway+/Runway DDR buses with I/O devices controlled by Elroy PCI bridges.

Midrange servers from that time are based on the same processors (PA-8500 to 8700) but use the sophisticated Stretch chipset, a rather complicated setup with central system controller and links to separate processor and I/O controllers and PCI bridges. Main system bus is the Itanium bus, with converters for the processors’ Runway+/Runway DDR buses.

IV. Decline: 64-bit to Itanium in the 2000s. HP transitioned to a post-RISC phase in the 2000s, releasing the last PA-RISC 2.0 processors and introducing Itanium to its server and workstation lineup. System designs converged between PA-RISC and Itanium.

PA-RISC moved towards a server-only role in the early 2000s, with a variety of servers in the rp-range and the similar Superdome mainframe. The Superdome mainframes and similar servers are based on PA-8700 and PA-8800/PA-8900 processors and use the Cell chipset, similar to the Stretch, but more scalable. Systems are made up of cells, with their own central system/memory controller, I/O controller and PCI bridges.

The last PA-RISC systems before the mainstream advent of the Itanium VLIW architecture in the mid-2000s use PA-8800/PA-8900 processors, followed by several generationis of Itanium systems. Both use the HP zx1 chipset, conceptually similar to Astro systems but with higher datarates and options, based on Itanium 2/McKinley buses.

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Old content

Several pages with older and abandoned PA-RISC content are kept on this site for archival reasons . They are listed on Archived PA-RISC pages. There is also a page on official HP documents that have since disappeared from the web.

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