PA-RISC Architecture

Spectrum
PA-RISC 1.0
PA-RISC 1.1
PA-RISC 2.0
PA-WideWord
TLB
Superscalar
MAX-1/MAX-2

PA-RISC is a Reduced Instruction Set Computing (RISC) architecture developed by Hewlett Packard in the 1980s, called Precision Architecture. PA-RISC was used until the mid-2000s in technical HP Unix workstations and servers, HP 9000. There were three versions of PA-RISC architecture, from 32-bit to 64-bit, and at least sixteen PA-RISC processors.

Version	Bits	Instructions	Features	Processors	Years
Spectrum	32-bit	140 beyond	Development	R&D	1982—1986
PA-RISC 1.0	32-bit	140 RISC	Original	TS-1, NS-1, NS-2, PCX	1986—1990
PA-RISC 1.1	32-bit	190 RISC	SMP, bi-endian Low-cost, MAX	PA-7000, PA-7100, PA-7200, PA-7100LC, PA-7300LC	1991—1996
PA-RISC 2.0	64-bit	RISC	MAX-2, on-chip cache, multicore	PA-8000, PA-8200, PA-8500, PA-8600, PA-8700, PA-8800, PA-8900	1996—2005
PA-WideWord	64-bit	VLIW/ILP	Super-parallel	PA-9000	90s-future

PA-RISC is based on the Precision Architecture, an offspring from HP research and development into RISC from the 1970s and 1980s. The aim of Precision Architecture was to replace 16-bit stack-based CPUs in HP 3000 servers and Motorola 68000 in HP’s Unix systems with a common system architecture.

HP Precision Architecture — Precision Architecture © HP 1986

PA-RISC architecture and instruction set were built from the ground up by HP engineers led by Joel Birnbaum, who moved from IBM to HP in the late 1970s. Previously at IBM, Birnbaum led the IBM 801 design, the first modern RISC processor. After an exodus of IBM’s key RISC designers, Birnbaum moved with a design team to HP and headed the development that ultimately led to PA-RISC.

Overall PA-RISC was a rather conservative RISC design for the 1980s, updated until the early 2000s. HP described the Precision Architecture as the result of years of studying RISC:

Reduced instruction set (simple, efficient instructions)
Instruction set is implemented in hardware (hardwired) and not microcoded.
Instruction size is fixed length and fixed format — one word (32-bit), which facilitates pipelining
Only three addressing modes: long/short displacement and indexed.
Load/store design: Only load and store operation access the memory, computational instructions do not.
Single cycle operation: Many simple and frequently used instructions execute in just one cycle, more complex computation are assigned to assist processors or software algorithms.
Optimizing compilers

The instruction set was tested widely by HP scientists on a wide range of programs with billions of instructions (in the 1980s!) to identify PA-RISC candidates – only instructions that could add value were selected.

HP added a few complementary features to increase flexibility and performance: Extended addressing, co- and multi-processor support and memory-mapped I/O. PA-RISC supported very wide adressing from the beginning and was designed as a SMP-capable architecture, with memory-mapped I/O simplifying the overall design.

Compared to other RISC architectures, original PA-RISC was rather simple and unspectacular — it had limited extra features but remained always at competitive speeds, especially in Floating Point and multiprocessing.

PA-RISC was implemented almost exlusively in HP processors, from early versions in TTL and NMOS in the 1980s to more modern integrated 32-bit and 64-bit RISC processors. HP was the first to include multimedia extension in commercially available microprocessors, MAX-1 in the PA-7100LC and MAX-2 64-bit in the PA-8000 for vector operations.

HP was late in bringing PA-RISC to 64-bit with PA-8000, a conservative CPU design.

Spectrum

During development, PA-RISC, the Precision Architecture, was called Spectrum at HP Labs in Palo Alto, where it was forged in laboratories based on experimental data to achieve a simple architecture. A talk given be Joel Birnbaum laid this out in 1986.

Design objectives for Spectrum, and then PA-RISC, were: leadership in price/performance, migration path from current HP products, unified scalable architecture. Spectrum was planned to be scalable from single chips up to mainframe machines with constant compatibility for programs

In the early 1980s, when HP Labs was developing the Precision Architecture (Spectrum), RISC had not been commercially successful yet, caused by incompatibility with software written for previous CISC architecture. The advantages of RISC vs. CISC were hotly debated at the time, with HP doing fundamental research on performance factors. This resulted, in HP’s words, in many innovations in PA-RISC, such as a comparable path length to conventional machines but superior throughput.

Hewlett-Packard’s Involvement in reduced instruction set computers (RISC) began in the early 1980s when a group was formed to develop a computer architecture powerful and versatile enough to excel in all of Hewlett-Packard’s markets including commercial, engineering, scientific, and manufacturing.

Spectrum had 140 instructions, a fraction of then current CISC designs but more than contemporary RISC platforms – specified really by the compiler people. Most instructions were single-cycle with only some multi-cycle instructions required for languages such as COBOL and FORTRAN. Important for the Precision Architecture were fast control and data paths without microcode, resulting in fewer transistors needed, and high speed registers, with 32 general purpose identified as optimal.

After 18 months of iterative, measurement -oriented evaluation of what computers do during application execution, the group produced an architecture definition known today as Precision Architecture RISC, or PA-RISC.

HP designed a few beyond RISC features into PA-RISC: very large address space (48-bit direct addressing for 64-bit virtual), split instruction and data caches, high-bandwidth internal buses, memory mapped I/O for high-speed devices of the future, precision interrupts for real-time response and optimized I/O bus interfaces to enable easy bus converters.

As HP fabbed VLSI chips inhouse at the time (and kept doing that until the 1990s), it touted expansion possibilities of the CPU through support chips such as FPU and SMP possibilities.

PA-RISC 1.0

PA-RISC 1.0 was the first commercial implementation of HP Spectrum research on RISC and Precision Architecture. PA-RISC 1.0 is 32-bit with a single instruction and data bus and 140 instructions, more than contemporary RISC designs. PA-RISC later moved to a Harvard architecture with seperate instruction and data buses.

PA-RISC 1.0 has thirty-two 32-bit integer general purpose registers (GR0-GR31), seven shadow registers (SR0-SR6) for fast-interrupts and thirty-two 64-bit Floating Point registers, which could be combined to 64 32-bit and 16 128-bit. The FPU can execute Floating Point instructions simultaneously to the ALU.

The PA-RISC 1.0 architecture and first four PA-RISC processors were designed primarily with multi-user systems and their demands on mind – I/O, memory and integer operations.

Processors based on PA-RISC 1.0 were implemented in a multitude of fabrication technologies – TTL, NMOS, CMOS for the early PA-RISC CPUs during the 1980s.

TS-1: First PA-RISC processor, on TTL boards
NS-1: Single NMOS chip with eight VLSI chips
NS-2: Longer pipeline, bigger caches and TLB
PCX: First PA-RISC processor in CMOS

Addressing in PA-RISC 1.0 was 48-bit wide, later on expanded to 64-bit with the introduction of the PA-8000 line in PA-RISC 2.0.

In the late 1980s, there were a number of groups that were looking for ways to make Hewlett-Packard more successful in the highly competitive workslation market. These groups realized the need for better floating-point performance and virtual memory management in PA-RISC to produce a low-cost, high-performance, PA-RISC-based workstation product, which eventually led to PA-RISC 1.1 and the first workstation processors.

PA-RISC 1.1

The Precision Architecture was extended to PA-RISC 1.1 in 1991, with PA-7000 being the first CPU with now 190 instructions. The modifications were based on years of experience with PA-RISC and PRISM from Apollo Computers, suggested extensions to the [PA1.1] architecture were heavily scrutinized and only accepted after their benefits could be validated. The result was a small but significant set of extensions to PA-RISC now known as PA-RISC 1.1.

With PA-RISC 1.1, HP tried to develop PA-RISC into a more engineering-friendly architecture, to grow from business- and transaction-oriented use cases of the 1980s (that needed I/O and integer operations). Major changes in PA-RISC 1.1 included:

Floating Point: Additional and improved floating-point instructions (Save states, store instructions, FTEST, multiply instructions, FP exceptions) and more FP registers (from 16 to 32 double-precision 64-bit FP) – especially for technical and engineering workloads.
Integration: PA-RISC 1.1 were far more integrated – the FPU was now on-chip, memory and I/O controllers in some cases as well, as were multimedia-extensions
Virtual Memory: D
Cache: Separation instruction and data caches through two ALU ports; cache path was enhanced from 32-bit to 64-bit; cache flush instructions; Cache hints
Graphics Performance: Block TLB and DMA from graphics to main memory (via the MIOC/MSBC) and color interpolation
Bi-Endian: PA-RISC 1.1 processors from the PA-7100LC up added bi-endian support (rumored to have been added for Windows NT support). Prior PA-RISC chips were big-endian.
Other: Integration of general shadow registers and larger page size (4 KB) for TLB improvements;

Starting with the second PA-RISC 1.1 processor PA-7100, PA-RISC processors implemented superscalar instruction execution to execute up to two multiple instructions simultaneously (later 64-bit processors up to four-way). Other significant developments in PA-RISC 1.1 include the PA-7100LC and PA-7300LC processors (LC for low cost), which integrated the memory and I/O controller onto the processor die, on the PA-7300LC additionally the cache controller and first-level cache.

Five HP processors implemented PA-RISC 1.1:

PA-7000: The first PA-RISC 1.1 processor, two-chip implementation (CPU and FPC)
PA-7100: Single-chip (CPU and FPU), SMP-capable
PA-7100LC: Integrated chip (with memory controller), multimedia (MAX-1)
PA-7200: Fast CPU, glueless SMP, newer bus
PA-7100LC: Integrated chip, adds on-chip caches
Several PRO consortium members developed PA-RISC 1.1 CPUs: Hitachi, Winbond, Oki

PA-RISC 2.0

In 1996 PA-RISC was redesigned for 64-bit with PA-RISC 2.0 and the PA-8000 processor. Architectural changes were deep but PA-RISC remained compatible with 32-bit PA-RISC 1.1. PA-RISC 2.0 and the PA-8000 were actually introduced before the last 32-bit PA-RISC processor PA-7300LC shipped.

Main changes and features of PA-RISC 2.0:

All registers and functional units extended to 64-bit
Virtual address space extended to 64-bit
Physical address space is 40-bit on PA-8000 to PA-8600 (for 1 TB of addressable physical memory) and 44-bit (16 TB memory) on PA-8700 and later
Increase of the CPU functional units (ALU, FPU and load/store) from three to ten
Instruction-level parallelism to keep the functional units supplied with instructions
Out-of-Order (OoO) execution through the Instruction Reorder Buffer (IRB), which stores up to 28 computation and 28 load/store instructions and reorders execution on the fly. The IRB tracks interdependecies and branch prediction outcomesand is the key part in the OoO execution capability of PA-RISC 2.0.
FPMAC (Floating Point Multiply Accumulate) units

Later PA-8x00 processors of the 2000s did not introduce significant changes to PA-RISC architecture besides large on-chip L1 caches in the PA-8600 and the integrated of dual-core PA-8800 and PA-8900. Processors after the PA-8000 were mostly redesigns and extensions of that processor core.

Seven HP processors implemented PA-RISC 2.0:

PA-8000: The first 64-bit PA-RISC 2.0 processor
PA-8200: Improved logic and prediction, clock increase
PA-8500: Large on-chip L1 caches, fabbed at Intel
PA-8600: Clock increases
PA-8700: Stop-gap until Merced, fabbed at IBM
PA-8800: First dual-core PA-RISC processor
PA-8900: Slight upgrade, large caches

Post-PA-RISC

HP originally started research into Instruction Level Parallel Processing (ILP) and Very Long Instruction Word (VLIW) architectures much earlier at HP Research Labs, the outcome of which it coined Explicitly Parallel Instruction Computing (EPIC) in the 1990s.

In the 1990s, HP was still planning on extending the PA-RISC architecture after 64-bit PA-RISC 2.0 into something called PA-WideWord (PA-WW) and Super Parallel Precision Architecture (SPPA), integrating research on ILP and VLIW architectures in a new set of processors beginning with PA-9000.

However, in mid-1990s on a parallel track to 64-bit PA-RISC and PA-WideWord, HP joined forces with Intel to commercialize ILP and VLIW in a brand new architecture. Both HP and Intel contributed R&D efforts and assets, resulting in what was called HP EPIC, Itanium and Intel IA64 architecture to revolutionize computing.

Eventual processors using this architecture were delayed several times and shipped only in early 2000, hindering building the Itanium platform and ecosystem and necessating a parallel development of PA-RISC for multiple years.

Since the early-2000s HP sold two lines of Unix computers and servers in parallel — having both PA-RISC 2.0 and Itanium computers with HP-UX. These competition was apparent in the Integrity servers — with the rp servers (PA-RISC) and rx servers (Itanium) that were very similar in performance and price.

HP’s post-PA-RISC designs were not the success many hoped for and HP soon after switched to standard Intel x86 fare in the late 2010s, keeping HP-UX and Itanium on life support for a few years. All the while having acquired Compaq with Digital Alpha and OpenVMS, another competing architectures.

Pre-PA-RISC

The predecessor of PA-RISC in the early 1980s was the HP FOCUS architecture from the HP 9000 Series 500. FOCUS was a stack architecture, with 230 instructions both 32 bits and 16 bits wide, a segmented memory model, and no general purpose programmer-visible registers. There are thirty-nine 32-bit registers in the CPU hardware, thirty-one internal 32-bit general purpose registers, two 32-bit ALU registers, and others.

Transition Lookaside Buffer (TLB)

Translation Lookaside Buffers are hardware structures for virtual-to-physical memory address translations which takes virtual page numbers and returns the corresponding physical page number. PA-7000 was the last PA-RISC processor with seperate instruction and data TLB, all later PA-RISC 1.1 and 2.0 processors had combined TLBs. Older PA-RISC 1.0 processors had huge TLBs, even for today’s standards.

TLB handling

PA-RISC TLB
CPU	TLB entries
PA-7000	96 I/96 D
PA-7100	120
PA-7100LC	64
PA-7200	120
PA-7300LC	96
PA-8000	96
PA-8200	120
PA-8500	160
PA-8600	160
PA-8700	240
PA-8800	2×240
PA-8900	2×240
Hitachi PA/50	32 I/64 D
Hitachi HARP-1	128 I/128 D
TS-1	4096 I/D
NS-1	4096 I/D
NS-2	16384 I/D
CMOS26B (PCX)	8192 I/D

Translation and miss handling in PA-RISC TLBs is as follows:

PA-RISC 1.1: If a virtual address has to be translated to a physical address, the corresponding TLB is searched for an entry matching the Virtual Page number. If an entry is found, the 20-bit Physical Page number, delivered by the TLB, is concatenated with the original 12-bit page offset to the build up the 32-bit absolute physical address.
Hardware: If the CPU implementation provides a hardware TLB miss handler, it attempts to find the virtual-to-physical translation in the Page Table. If successful, the translation and protection fields are inserted in the TLB. If not successful, an interruption occurs so the software miss handler can complete the translation.
Software: If software TLB miss handling is implemented, a TLB miss fault interruption routine performs the translation. It inserts the translation and protection fields in the TLB and afterward restarts the interrupted routine, in which the TLB miss occurred.

Block Transition Lookaside Buffer (BTLB)

Similar to the TLB, the BTLB provides virtual-to-physical address translations. The BTLB however maps large address ranges rather that single pages as the TLB. These large address ranges are block translations and therefore stored in the Block Translation Lookaside Buffer. These block translations are useful for virtual address ranges that do not get paged in or out.

BTLBs were only implemented on 32-bit PA-RISC processors (PA-7x00), 64-bit PA-RISC instead implemented variable page sizes, thus any entry can be of >4k mapping.

Superscalar PA-RISC

Every PA-RISC processor from the PA-7100 on implements superscalar execution. Superscalar processors decode, dispatch and execute multiple instructions per cycle if dependencies between the instructions permit. This is possible if the instruction stream contains independent instructions.

Superscalarity
PA-RISC	CPU	Scalar	Fetch path	Units
PA-RISC 1.0	TS-1, NS-1, NS-2, PCX	1-way	32-bit	1+1
PA-RISC 1.1a	PA-7000	1-way	32-bit	1+1
PA-RISC 1.1b	PA-7100	2-way limited	64-bit	2
PA-RISC 1.1c PA-RISC 1.1d PA-RISC 1.1e	PA-7100LC PA-7200 PA-7300LC	2-way	64-bit	3
PA-RISC 2.0	PA-8000, PA-8200, PA-8500, PA-8600, PA-8700	4-way	128-bit	10
PA-RISC 2.0	PA-8800, PA-8900	2×4-way	2×128-bit	2×10

Superscalarity can be gained from a decoupled floating point unit (FPU) which executes floating point operations indepently from the integer ALU. More advanced superscalarity allows parallel load/store operations, integer calculations, needing a more complex CPU design that analyzes instructions branches.

Instructions proceed together through the execution pipeline, instruction bundling. Superscalar execution is functionally transparent to the software, the effects of any given instruction are the same whether it was executed as part of a bundle or alone.

Bundling rules are applied at run-time by the hardware; optimal performance may only be gained by proper ordering of the instructions so the processor can use its full superscalar potential. Restrictions are placed on instruction bundling in PA-RISC: Functional unit contention, Data dependencies, Control flow and special instruction restrictions.

For bundling purposes instructions are divided into classes:

PA-RISC superscalar instruction classes
Class	Description
FLOP	Floating point operation
LDST	Loads and stores
ALU	Integer ALU
MM	Shifts, extracts, deposits
NUL	Might nullify successor
BV	Branch Vectored (BV) local, Branch (BE) external
BR	Other branches
FSYS	FTEST and FP status/exception
SYS	System control instructions

PA-RISC 1.1 Superscalarity

PA-RISC processors had different superscalar capabilities: PA-7100 is two-way superscalar with one integer ALU and one FPU, PA-7100LC, PA-7300LC and PA-7200 are also two-way superscalar but with two ALUs and one FPU.

Processor	First instruction	Second instruction
PA-7100	ALU	+ FLOP
	LDST	+ FLOP
	FLOP	+ ALU/LDST/Branch
PA-7100LC PA-7300LC PA-7200	FLOP	+ LDST/ALU/MM/NUL/BV/BR
	LDST	+ FLOP/ALU/MM/NUL/BR
	ALU	+ FLOP/LDST/ALU/MM/NUL/BR/FSYS
	MM	+ FLOP/LDST/ALU/FSYS
	NUL	+ FLOP
	SYS	Never bundled

PA-RISC 2.0 Superscalarity

PA-RISC 2.0 superscalar capabilities still need to be described.

Multimedia Acceleration MAX-1 and MAX-2

MAX-1 (32-bit)

MAX-1 are PA-RISC multimedia extensions from the 1990s introduced in the HP PA-7100LC processor and later PA-7300LC. HP aimed to enable contemporary PA-RISC workstations to provide real-time MPEG video decompression and playback at a rate of 30 frames/second without the need for a special DSP (digital signal processing) chip.

HP’ design process for the PA-7100LC processor in the early 1990s included for the first time multimedia benchmarks for analyzing optimizations in the instruction set design.

MAX-1 implementation used a small set of SIMD-MIMD instructions to faciliate the application of instructions on bundled subword data. Since these instructions use the same data paths and execution units within the processor as the regular instructions, the design team termed this intrinsic signal processing (ISP).

Sticking to conventional RISC principles, the design team decided against adding complex special-purpose instructions to the design but used existing facilities in the CPU, which were slightly modified to understand new, packed subword data.

In 1994, MAX-1 extensions made their way into the final PA-7100LC product and as such were the first SIMD instructions found in a general microprocessor. Less than 0.2 percent of the processor silicon area was used for MAX-1 additions and modifications, while allowing a very significant performance boost in affected applications.

As an example, the then-highend HP 9000 735/99 workstation with a 99 MHz processor and 512 KB cache achieved 18.7 FPS at MPEG decompression benchmarks — the new entry-level 712 workstation at 60 MHz and 64 KB cache achieved 26 FPS, an impressive feat for the time of 1990s information technology.

New MAX-1 multimedia instructions include: parallel add, parallel subtract, parallel shift left & add (multiply with integer), parallel shift right & add (division), parallel average.

MAX-2 (64-bit)

With the introduction of the new 64-bit PA-RISC 2.0 architecture in 1996, HP unveiled MAX-2, a new set of multimedia-oriented instructions aimed at using the processor’s resources more effectively for sub-word data. The basic components of the contemporary multimedia data were often represented as 8, 12 or 16-bit integers, for example audio sampling and pixel color depth.

Doing arithmetic with data of this length would waste an considerable amount of the processor’s execution capacities, a simple addition of 16-bit data would only use one quarter of the 64-bit wide integer units datapath. To remedy this situation, MAX allows for packing of these subword data into larger words near the processor’s natural word width (64-bit on PA-RISC 2.0 processors) and using parallel instructions on them. An example would be four 16-bit additions by the 64-bit adder on four 16-bit packed subwords.

The basic functionality from earlier 32-bit MAX-1 was taken over and four more instructions added for MAX-2. Additionally, due to the wider integer registers (now 64-bit) more subwords could be packed in one cycle, doubling the effective speed of these multimedia instructions. MAX-2 multimedia instructions include (new in MAX-2 are in bold): parallel add, parallel subtract, parallel shift left & add (multiply with integer), parallel shift right & add (division), parallel average, parallel shift right, parallel shift left, mix and permute.

MAX-2 debuted 1996 with the PA-8000 processor and later featured on all subsequent PA-RISC 2.0 processors (PA-8x00). In contrast to contemporary multimedia extensions, MAX-2 required only very little die space (0.1 percent on the PA-8000).