ASP PA-RISC Chipset

HP 9000 workstations and servers based on 32-bit PA-7000 and PA-7100 processors use the HP ASP chipset with the central HP Viper memory controller. There are two variants of HP ASP for workstations: HP Coral or Cobra I/O subsystem is the original ASP (first), while HP Hardball is the second version ASP2.

ASP

ASP includes separate chips to provide the I/O subsystem with several third-party components. Some HP 9000 800 servers use a partial implementation of ASP.

HP ASP chipset
HP Viper memory and I/O controller (MIOC) or memory and system bus controller
NCR 53C700 8-bit Narrow single-ended SCSI-2
Intel 82596DX 10 Mbit Ethernet controller, and Intel 82501AD Ethernet transceiver, media auto-selection
EISA bridge based on the Intel 82350 chipset
Domain keyboard controller
WD 16C552 parallel and NS 16550A compatible serial
Intel 8042 microprocessor
512 KB EPROM Boot ROM, 8 KB EEPROM for storing system configuration status etc.
ASP: 25-33 MHz chipset clock frequency on a 160-pin QFP chip
VSC interface to system main bus, 32-bit, to the Viper memory controller
GSC interface to main I/O bus, also sometimes called SGC

ASP2

Hardball is the second version ASP2 (below), an improved design with fast/wide SCSI and FDDI networking used in HP 9000 735 and 755 workstations:

HP Shortstop: main bus and memory interface, a Viper variant
HP Cutoff: main address controller
NCR 53C720 16-bit Fast-Wide differential SCSI-2
AMD Formac Plus Am79C830 FDDI controller
Stereo/CD quality audio
Two 32-bit device data buses, a variant of GSC bus: one attaches to LAN and FDDI, the other to two SCSI controllers, audio and other I/O devices

Viper

HP Viper is the memory and I/O controller (MIOC), also called memory and system bus controller (MSBC), on HP computers with 32-bit PA-7000 and PA-7100 PA-RISC processors. Viper is similar on both platforms and sometimes counted into the HP ASP chipset, in which it was always used as memory and I/O controller.

Viper as MIOC handles all memory and I/O traffic between processor and the rest of the system.

Viper attaches with 32-bit multiplexed address/data bus PBus to the CPU
Memory attaches directly to Viper, with multiplexed 64-bit ECC
VSC system main bus attaches to Viper, 32-bit on PA-7000, 64-bit on PA-7100
I/O attaches with bus adapters to VSC bus
Viper is also called MIOC, PMI or PIC
On SMP systems either each CPU has its own MIOC which share a SMB bus and memory, or two CPUs share one MIOC
Viper MIOC/MSBC: 9,5×9,5 mm² die, 185,000 FETs, 0.8µ, CMOS26B in 272-pin CPGA
Shortstop (ASP2) MIOC/MSBC: 408-pin PGA
SBI system bus interface: two chips in 0.8µ, CMOS26B 100-pin QFP
Low-cost version on the 705/710 workstations: two separate chips, each 7,0×7,0 mm² die, 1.0µ, two-layer metal CMOS34 in 160-pin QFP

Used in

HP 9000 705, 710, 715, 725, 720, 730, 750, 742i, 745i, 747i workstations
ASP2: HP 9000 735, 755
HP 9000 Nova servers (F, G, H, I-Class)
HP 9000 890, T500, T520 servers
Mitsubishi ME workstations
Hitachi 3050RX, 9000V workstations

Documentation

Hardball I/O Subsystem, External Reference Specification (.pdf), Hewlett-Packard Company (September 1991, Version 1.1)
High Performance PA-RISC Snakes Motherboard I/O , Hewlett-Packard 1993, bitsavers
Hewlett-Packard Journal December 1992 archive.org
- The EISA standard for the HP 9000 Series 700 workstations, page 78 (Vicente Cavanna and Christopher S. Liu)
Hewlett-Packard Journal August 1992 archive.org
- Midrange PA-RISC Workstations with Price/Performance Leadership, page 6 (Andrew J. DeBaets and Kathleen M. Wheeler)
- HP 9000 Series 700 Workstation Firmware (IODC, PDC) page 9 (Deborah A. Savage)
- VLSI Circuits for Low-End and Midrange PA-RISC Computers, page 12 (Craig A. Gleason et al.)
- HP 9000 Series 700 Input/Output Subsystem, page 26 (Daniel Li and Audrey B. Gore)
- Design Verification of the HP 9000 Series 700 PA-RISC Workstations, page 34 (Ali M. Ahi et al.)
- Mechanical Design of the HP 9000 Models 720 and 730 Workstations, page 43 (Arlen L. Roesner and John P. Hoppal)
- Meeting Manufacturing Challenges for PA-RISC Workstations, page 49 (Spencer M. Ure et al.)