PA-RISC Chipsets
ASP chipset
HP 9000 workstations and servers based on the 32-bit PA-7000 and PA-7100 processors use the ASP chipset together with the Viper memory controller. Being an integrated chipset, ASP includes separate chips to provide the I/O subsystem and contains several modules from third-party vendors. Some HP 9000 800 servers use a partial implementation of ASP.
- VSC interface to system main bus, 32-bit, to the Viper memory controller
- GSC interface to main I/O bus, also sometimes called
SGC
- NCR 53C700 8-bit Narrow single-ended SCSI-2
- Intel 82596DX 10 Mbit Ethernet controller, and Intel 82501AD Ethernet transceiver, media auto-selection
- EISA bridge based on the Intel 82350 chipset
- Domain keyboard controller
- WD 16C552 parallel and NS 16550A compatible serial
- Intel 8042 microprocessor
- 512 KB EPROM Boot ROM, 8 KB EEPROM for storing system configuration status etc.
- 25-33 MHz chipset clock frequency on a 160-pin QFP chip
There are two variants of ASP for workstations: Coral or Cobra I/O subsystem
is the original ASP,
while Hardball
is the second version ASP2, an improved design with fast/wide SCSI and FDDI networking, used on the 735/755 workstations:
- NCR 53C720 16-bit Fast-Wide differential SCSI-2
- AMD Formac Plus Am79C830 FDDI controller
- Stereo/CD quality audio
- Two 32-bit device data buses, a variant of GSC bus: one attaches to LAN and FDDI, the other to two SCSI controllers, audio and other I/O devices
- ASP2 consists of two separate chips: Shortstop, main bus and memory interface, and Cutoff, the main address controller
Viper
Viper is the memory and I/O controller MIOC on systems with PA-7000 and PA-7100 processors. The chip is similar on both, and sometimes counted into the ASP I/O chipset. It handles all memory and I/O traffic between the processor and the rest of the system.
- Viper attaches with 32-bit multiplexed address/data bus PBus to the CPU
- Memory attaches directly to Viper, with multiplexed 64-bit ECC
- VSC system main bus attaches to Viper, 32-bit on PA-7000, 64-bit on PA-7100
- I/O attaches with bus adapters to VSC bus
- Viper is also called MIOC, PMI or PIC
- On SMP systems either each CPU has its own MIOC which share a SMB bus and memory, or two CPUs share one MIOC
- 9,5×9,5 mm2 die, 185,000 FETs, 0.8µ, CMOS26B in 272-pin CPGA
- Newer/different Viper design: 0.8µ, CMOS26B in 408-pin PGA
- SBI system bus interface: two 100-pin QFP chips
- Low-cost version on the 705/710 workstations: two separate chips, each 7,0×7,0 mm2 die, 1.0µ, two-layer metal CMOS34 in 160-pin QFP
Used in
- 705, 710, 715, 725, 720, 730, 750, 735, 755, 742i, 745i, 747i
- Nova servers (F, G, H, I-Class)
- 890, T500, T520
- Mitsubishi ME/R7200, ME/S7200, ME/R7300, ME/S7300, ME/R7500, ME/S7500
- Hitachi 3050RX 220, 230, 310S, 320, 330, 430, 440, 9000V V735/125, VT500
References
- Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal) pp. 6-11
- VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) Craig A. Gleason (August 1992: Hewlett-Packard Journal) pp. 12-22
- High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) Craig Fink et al (August 1992: Hewlett-Packard Journal) pp. 56-63
- Hardball I/O Subsystem, External Reference Specification (.pdf) Hewlett-Packard Company (September 1991, Version 1.1)
- The EISA standard for the HP 9000 Series 700 workstations (.pdf) Vicente Cavanna and Christopher S. Liu (December 1992, Hewlett-Packard Journal) pp. 78
- Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
- VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)
- High-Performance Design for Low-Cost PA-RISC Desktops (.pdf) pp. 56-63 Craig Fink et al (August 1992: Hewlett-Packard Journal)