Cell PA-RISC Chipset

HP Cell is a crossbar chipset used in 64-bit HP PA-RISC rp servers and some HP Superdome mainframe computers. The central component, Central Electronics Complex (CEC), interconnects individual system and processor cells via central crossbars. Cell boards were seated in the backplane of the systems for cell-to-cell links and I/O functionality.

HP Cell Controller (CC) is the central chipset of each cell. CC connects local processors and memory of cells to SBA I/O links and XBC crossbar. XBC is the chip that provides the main backplane function. Different backplanes can be tied together through links in XBCs with high-bandwidth low latency connections.

M2 are HP Cell memory controllers on each cell board. There are eight M2 controllers in two banks on each CC. Requests and addresses are sent directly from CC to memory, with data returning through M2s.

RIO is the master I/O controller in HP Cell, called SBA. Each SBA provides sixteen 12-bit links called ropes to which slave I/O controllers connect, the LBAs. These LBAs are Elroy PCI bridges that convert the links from the SBA into PCI buses.

Core I/O is a card set that provides standard I/O functions and plugs into PCI-64 or special slots to provide third-party I/O functions. Different cards were availaible: MP/SCSI card and LAN/SCSI, for the following devices:

Several buses were used in Cell: Runway+ processor bus for up to four processors at 8.0 GB/s. Memory bus to the M2, for up to two memory banks with 4.0 GB/s peak The SBA I/O links to the off-cell SBA have 2.0 GB/s peak, the XBC link to the crossbar for cell-to-cell communication 8.0 GB/s peak.

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