PA-RISC information - since 1999

PA-RISC Chipsets

Cell chipset

Cell is a crossbar chipset used in HP 9000 PA-RISC Integrity servers and some Superdome mainframe computers. The Central Electronics Complex CEC interconnects individual system and processor cells via central crossbars. The cell boards were seated in the backplane of the system, which provided the cell-to-cell links and I/O functionality.

The CC Cell Controller is the central chipset at the core of each cell. It connects local processors and memory on cells to the SBA I/O links and the XBC crossbar. XBC is the crossbar ASIC that provides the main backplane function, each backplane supports up two four cell modules. Different backplanes can be tied together through links through the XBCs with a high-bandwidth, low/latency connection.

M2 are the main memory controllers and converters on each cell board. There are eight M2 controllers that attach in two banks to each CC. Requests and addresses are sent directly from the CC to memory, with the data returning through the M2s.

RIO is the master I/O controller, also called SBA. The central I/O part of the main chipset, with one SBA reserved for each cell/CC, located on the (I/O) backplane. Each SBA provides sixteen 12-bit links called ropes to which slave I/O controllers connect, the LBAs. These LBAs are Elroy PCI bridges that convert the links from the SBA into PCI buses.

Core I/O is a card set that provides standard I/O functions and plugs into PCI-64 or special slots to provide third-party I/O functions. Distinct cards were availaible: MP/SCSI card and LAN/SCSI, among others.

Several buses were used in Cell: Runway+ processor bus for up to four processors at 8.0 GB/s. Memory bus to the M2, for up to two memory banks with 4.0 GB/s peak The SBA I/O links to the off-cell SBA have 2.0 GB/s peak, the XBC link to the crossbar for cell-to-cell communication 8.0 GB/s peak.

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