PA-RISC information - since 1999

PA-RISC Chipsets

Early designs

Early 32-bit PA-RISC systems, such as the 1980s TS-1, NS-1, NS-2 and PCX, used custom designs based on the SIU/SPI main bus interfaces and the SMB bus. The computing and I/O units consisted of a large number of individual chips to form the central chipset and used the CIO and HP-PB I/O buses. The first PA-RISC 1.0 processors used external support chips to attach the CPU to memory and I/O. This functionality was later integrated into single chips and then moved to the CPU altogether.

Systems using these early designs, in various, slightly different variants:

View a system-level illustration (ASCII).

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