Early 32-bit PA-RISC systems, such as the 1980s TS-1, NS-1, NS-2 and PCX, used custom designs based on the SIU/SPI main bus interfaces and the SMB bus. The computing and I/O units consisted of a large number of individual chips to form the central chipset and used the CIO and HP-PB I/O buses. The first PA-RISC 1.0 processors used external support chips to attach the CPU to memory and I/O. This functionality was later integrated into single chips and then moved to the CPU altogether.
- SIU or SPI system interface unit attaches the CPU to the SMB system main bus
- NS-1 Two cache controller units CCU0 and CCU1
- NS-2 Two CCUs cache controller units ICCU and DCCU
- PCX Three CMUX cache multiplexers
- Physical address space of 29-bit to support up to 512 MB main memory
- System Main Bus SMB is the central bus, to which CPU, memory and I/O buses attach with 64-bit at 25-30MHz.
- Memory is attached to the SMB main bus
- Central Bus or Midbus CTB attaches the I/O via bus converters to SMB, 32-bit at maximum of 10 MHz
- CIO buses for I/O devices attach via adapters to CTB, 16-bit at 4 MHz, I/O expansion cards plug into CIO slots
Systems using these early designs, in various, slightly different variants: