PA-RISC information - since 1999

PA-RISC Chipsets

LASI chipset

PA-7100LC and PA-7300LC systems use the highly integrated LASI chipset, which combines most functions and I/O on a single chip and an on-CPU MIOC memory controller.

LASI was primarily designed for cost-reduction while still providing most I/O functions. It was used as the main controller in most PA-7100LC and PA-7300LC systems, while later 64-bit PA-8x00 systems used LASI for complementary I/O functions. The primary cost reductions were achieved by integrating the major I/O subsystems into a single chip, like LAN SCSI. and some designed specifically for LASI. The LC CPUs integrate the external memory and I/O controller MIOC onto the processor with memory and cache directly attaching to it.

A typical system design with one of the 32-bit LC Low Cost processors PA-7100LC and PA-7300LC wht GSC main system bus would look like this:

  1. MIOC, main memory and I/O controller, directly integrated on the CPU
    • Execution units and internal caches attach on-chip to the MIOC
    • External cache and memory attach to MIOC
  2. GSC, system main bus, attaches to MIOC and I/O controllers
    • Attaches via 32-bit
    • PA-7300LC systems use extended GSC+
  3. I/O adapters attach to GSC
    • LASI chipset
    • Some video adapters directly attach to GSC
    • I/O slots extend GSC
    • Bus adapters, including EISA, VME and PCI, attach to GSC

View a system-level illustration (ASCII).

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Memory and I/O Controller (MIOC)

The Memory and I/O Controller in the PA-7100LC and PA-7300LC processor integrates DRAM/cache and I/O controller onto the processor die. It is similar on both CPUs, with the PA-7300LC MIOC having wider data paths to L2 cache and RAM and supporting the advanced GSC+ bus over the older GSC.

The integrated memory controller requires only buffers and DRAM modules to build up the complete memory subsystem. The PA-7300LC memory controller includes a Second Level Cache Controller SLC, which provides an optional L2 cache, ranging from 32 KB to 8 MB. It shares the data bus with the DRAM subsystem, so it has the same width and same optional SEDC error control.

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Wax is a secondary I/O controller complimentary to the LASI chipset. It implements various secondary I/O functions and acts as a I/O bus to GSC adapter for different external buses as EISA, HP-HIL and HP-IB. Most systems use it to complement LASI with other required I/O functions that were previously implented in diverse I/O ASICs. It is implemented in the same process and package as LASI.

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Used in

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  1. 712 I/O Subsystem ERS (External Reference Specification) — LASI ERS Hewlett-Packard Company (February 1993, Revision 1.1)
  2. An I/O System on a Chip Thomas V. Spencer et al (April 1995, Hewlett-Packard Journal)
  3. PA7100LC ERS (External Reference Specification) (.pdf) Hewlett-Packard Company (1999)
  4. The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment Mick Bass et al (April 1995: Hewlett-Packard Journal. Accessed May 2009)
  5. PA7300LC ERS (External Reference Specification) (PDF, 716 KB) Hewlett-Packard Company (1996)
  6. The PA-7300LC: the first System on a Chip ( mirror) Tom Meyer (1996: Presentation for Microprocessor Forum 1995)
  7. External Reference Specification (ERS) for the Wax I/O ASIC Hewlett-Packard Company (May 1993, version 1.0 redacted)