Stretch PA-RISC Chipset

HP Stretch was a 64-bit HP PA-RISC system design for midrange servers based on PA-8500 to 8700 processors, a complicated setup with a central system controller and links to processor and I/O controllers and PCI bridges. The main system bus is an HP Itanium bus, with converters for the processor Runway+/Runway DDR buses. There are four main components, and the following buses used:

HP Prelude memory controller connects the main memory to two system buses.
HP DEW Runway ports/converters convert the system buses into Runway buses for the PA-8500 and upwards CPUs — two CPUs share one DEW.
HP IKE I/O controllers attach PCI bridges via I/O links to the system bus.
HP Elroy PCI bridges convert the I/O channels from IKE I/O controllers into PCI buses

        CPU0    CPU1 CPU2    CPU3   CPU4    CPU5 CPU6    CPU7
         |       |    |       |      |       |    |       |
  2.1GB/s|  ___  |    |  ___  |      |  ___  |    |  ___  |2.1GB/s (each CPU)
         |_|DEW|_|    |_|DEW|_|      |_|DEW|_|    |_|DEW|_|
           |___|        |___|          |___|        |___|
   _____     |            |    _____     |            |    _____ 
  |     |    |   2.1GB/s  |   |     |    |   2.1GB/s  |   |     |
  | IKE |=====================Prelude=====================| IKE |
  |_____|                     |     |                     |_____|
     |                        |_____|                        |   
     |                         ||||                          |
     | 12x265MB/s              |||| 4x2.1GB/s                | 12x265MB/s
     | (3.2GB/s)               |||| (8.5GB/s)                | (3.2GB/s)
     |                     ============                      |
     |                     ============                      |
     |                     ============                      |
     |                     ============                      |
     |                        Memory                         |
     |                                                       |
  =============================                    ======================
  |   |   |   |  ||  ||  ||  ||                    ||  ||  ||  ||  ||  ||
 265  |   |   | 530  ||  ||  ||                   530  ||  ||  ||  ||  ||
 MB/s |   |   | MB/s ||  ||  ||                   MB/s ||  ||  ||  ||  ||
  |   |   |   |  ||  ||  ||  ||                    ||  ||  ||  ||  ||  ||
  |   |   |   |  ||  ||  ||  ||                    ||  ||  ||  ||  ||  ||
 LBA LBA LBA LBA LBA LBA LBA LBA                   LBA LBA LBA LBA LBA LBA
  |   |   |   |  ||  ||  ||  ||                    ||  ||  ||  ||  ||  ||
  |   |   |   |  ||  ||  ||  ||                    ||  ||  ||  ||  ||  ||
 PCI PCI PCI PCI PCI PCI PCI PCI                   PCI PCI PCI PCI PCI PCI
 2x  2x  2x  2x  4x  4x  4x  4x                    4x  4x  4x  4x  4x  4x
  |   |
 Core Core
 I/O  I/O

   PCI slots/buses:
   PCI 4x -- PCI 64-bit/66MHz (533MB/s)
   PCI 2x -- PCI 64-bit/33MHz (266MB/s)

   LBA connections/downlinks:
   ||   two ropes -- 530MB/s
   |    one rope  -- 265MB/s

Exemplary HP Stretch system architecture in N4000 rp7400

Prelude

HP Prelude is the memory controller of PA-RISC systems with Stretch chipset and connects up to 16 pairs of SDRAM memory via four memory buses to two system buses. The main buses are HP Itanium buses, in preparation of the early 2000s HP shift from PA-RISC to Itanium.

Prelude consists of three VLSI chips: one address controller and two data controllers; each data controller drives two multiplexed 64-bit memory buses:

Two system buses, each 2.1 GB/s peak with 4.3 GB/s aggregate
Up to four memory buses, each 2.1 GB/s peak with 8.6 GB/s aggregate to the memory
Both memory and system buses are Itanium/Merced buses at 133 MHz DDR with 64-bit width, ECC-protected
System main buses connect to the CPU bridges (DEW) and I/O controllers (IKE)

DEW

HP DEW is the Runway CPU bridge for 64-bit PA-RISC systems using the HP Stretch chipset. It attaches the Runway-based PA-8500, PA-8600 and PA-8700 PA-RISC processors to Itanium ed system man buses. Each pair of CPUs share one DEW port converter. Common configurations include one to four DEWs for up to eight processors.

CPU side: Runway+/Runway DDR processor bus for up to two PA-8x00 processors with peak bandwidth of 2.1 GB/s
System side: Itanium system bus at 133 MHz, with 2.1 GB/s peak

IKE

HP IKE is the I/O controller on 64-bit PA-RISC systems with HP Stretch chipset. IKE is the central memory controller that provides one or two system buses, to which CPUs and I/O attach. Each system bus has one IKE I/O controller that connects to several I/O controllers (Elroy bridges), which in turn provide PCI buses.

The connection between IKE and each slave I/O controller is one or two 12-byte wide I/O links (I/O ropes), which can be combined into twin I/O channels for so-called Twin-Turbo PCI slots/buses.

System side connects to system main bus, a Itanium bus at 133 MHz, with 2.1 GB/s peak
I/O side attaches to up to twelve 12-byte wide 266 MB/s I/O links
Each PCI slot has its own PCI controller and bus
HP Elroy PCI bridges convert the I/O channels into PCI buses

Used in

The HP Stretch chipset was used only in few HP PA-RISC systems of the early 2000s.

HP 9000 L1500 (rp5430), L3000 (rp5470) servers
HP 9000 N4000 (rp7400) servers

Documentation

hp server rp7400 system architecture and design guide, Hewlett-Packard Company alimar (February 2002, product number 5981-0154EN, mirror)
hp server rp5400 series entry-level UNIX servers technical whitepaper (URL gone)