PA-RISC information - since 1999

PA-RISC Chipsets

Stretch system design

Stretch was a 64-bit HP PA-RISC system design for midrange servers based on PA-8500 to 8700 processors, a complicated setup with a central system controller and links to processor and I/O controllers and PCI bridges. The main system bus is an Itanium bus, with converters for the processors’ Runway+/Runway DDR buses. There are four main components, and the following buses used:

» For illustration view a system-level description of the N4000 server (Stretch-based).

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Prelude is the memory controller of systems with the Stretch chipset and connects the up to 16 pairs of SDRAM memory via four memory buses to two system buses. The main buses are in fact Itanium/Merced buses in preparation of the HP shift from PA-RISC to Itanium. Prelude consists of three VLSI chips: one address controller and two data controllers; each data controller drives two multiplexed 64-bit memory buses:

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DEW is the Runway CPU bridge for systems based on the Stretch chipset. It attaches the Runway-based PA-8500, PA-8600 and PA-8700 CPUs to the Itanum-based system man buses. Each pair of two CPUs share one DEW port converter. Common configurations include one to four DEWs for up to eight processors.

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IKE is the I/O controller on systems with the Stretch chipset. The central memory controller provides one or two system buses, to which CPUs and I/O attach. Each system bus has one IKE I/O controller that connects to several slave I/O controllers (Elroy PCI bridges), which in turn provide PCI buses. The connection between IKE and each slave I/O controller is one or two 12-byte wide I/O links (I/O ropes). I/O channels can be combined into twin I/O channels for so-called Twin-Turbo PCI slots/buses.

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