Stretch system design
Stretch was a 64-bit system design for midrange servers based on PA-8500 to 8700 processors,
a complicated setup with a central system controller and
links to processor and I/O controllers and PCI bridges.
The main system bus is an Itanium bus, with converters for the processors’ Runway+/Runway DDR buses.
There are four main components, and the following buses used:
- Prelude memory controller connects the main memory to two system buses.
- DEW Runway ports/converters convert the system buses into Runway buses for the PA-8500 and upwards CPUs — two CPUs share one DEW.
- IKE I/O controllers attach PCI bridges via I/O links to the system bus.
- Elroy PCI bridges convert the I/O channels from IKE I/O controllers into PCI buses
» For illustration view a system-level description of the N4000 server (Stretch-based).
Prelude is the memory controller of systems with the Stretch chipset and connects the up to 16 pairs of SDRAM memory via four memory buses to two system buses. The main buses are in fact Itanium/Merced buses in preparation of the HP shift from PA-RISC to Itanium. Prelude consists of three VLSI chips: one address controller and two data controllers; each data controller drives two multiplexed 64-bit memory buses:
- Two system buses, each 2.1 GB/s peak with 4.3 GB/s aggregate
- Up to four memory buses, each 2.1 GB/s peak with 8.6 GB/s aggregate to the memory
- Both memory and system buses are Itanium/Merced buses at 133 MHz DDR with 64-bit width, ECC-protected
- System main buses connect to the CPU bridges (DEW) and I/O controllers (IKE)
DEW is the Runway CPU bridge for systems based on the Stretch chipset. It attaches the Runway-based PA-8500, PA-8600 and PA-8700 CPUs to the Itanum-based system man buses. Each pair of two CPUs share one DEW port converter. Common configurations include one to four DEWs for up to eight processors.
- CPU side: Runway+/Runway DDR processor bus for up to two PA-8x00 processors with peak bandwidth of 2.1 GB/s
- System side: Itanium system bus at 133 MHz, with 2.1 GB/s peak
IKE is the I/O controller on systems with the Stretch chipset.
The central memory controller provides one or two system buses, to which CPUs and
Each system bus has one IKE I/O controller that connects to several slave I/O
controllers (Elroy PCI bridges), which in turn provide PCI buses.
The connection between IKE and each slave I/O controller is one or two
12-byte wide I/O links (I/O ropes).
I/O channels can be combined into twin I/O channels for so-called
- System side connects to system main bus, a Itanium bus at 133 MHz, with 2.1 GB/s peak
- I/O side attaches to up to twelve 12-byte wide 266 MB/s I/O links
- Each PCI slot has its own PCI controller and bus
- Elroy PCI bridges convert the I/O channels into PCI buses
- hp server rp7400 whitepaper (URL gone)
- hp server rp5400 series entry-level UNIX servers technical whitepaper (URL gone)