PA-RISC Chipsets
U2 and UTurn chipset
PA-RISC computers based on 32-bit and 64-bit processors with a Runway processor interface used a U2 or UTurn system design and chipsets. U2 and UTurn are the I/O adapters and MMC/SMC the memory controllers that each attach other subsystems to the main Runway processor bus. Also called IOAs, UTurn and U2 attach the GSC main system bus with devices and I/O to the Runway to the processors. This setup allowed HP to use a standard frontend with UTurn in different system designs with different backends to support memory or I/O technologies.
U2 is the variant for PA-7200 systems while all later systems with PA-8000 and PA-8200 processors use the UTurn follow-on.
- Runway bus interface to CPU/memory bus, 64-bit wide, 120 MHz, 960 MB/s peak bandwidth
- U2: Two GSC+/HSC I/O buses, peak bandwidth between 128 MB/s to 160 MB/s each
- UTurn: Two GSC-2 I/O buses, peak bandwidth 256 MB/s each
- Support for various frequencies on both sides on Runway and GSC
- Address translation from 32-bit GSC to 40-bit Runway addresses
- Interface to processor dependent hardware PDH on IOA A
- Hardware cache coherent I/O
- Real-time clock
- U2 is a 432-pin PGA chip, chip numbers: 1MM6-0004
A typical U2/UTurn system design and bus setup would look the following:
- Runway is the main processor and memory bus for 1-4 CPUs at 64-bit
- MMC is the main memory controller which attaches to Runway at 64-bit
- Memory attaches to MMC via slave Memory Controllers SMC and Data Multiplexers, 128-bit 60 MHz data and 39-bit 60 MHz address buses
- U2/UTurn I/O adapters attach the system bus to the Runway processor bus at 64-bit
- GSC+, the main system bus, attach to the U2/UTurn IOAs at 32-bit
- I/O adapters and slots attach to GSC+
- LASI chipset
- Video adapters
- I/O slots extend GSC
- Bus adapters, including EISA, VME and PCI, attach to GSC+
Used in
- C100, C110 (U2) C160, C180 (UTurn), C200, C240, C360 (UTurn)
- D-Class and R-Class
- J200, J210, J210XC (U2), J280, J282, J2240 (UTurn)
- K-Class
MMC/SMC
Most systems with a PA-7200, PA-8000 or PA-8200 processor use a combination of the MMC and SMC memory controllers to attach the main system memory to the Runway processor bus. The I/O is controlled by the U2/UTurn I/O adapters on the same Runway bus.
- Master Memory Controller MMC attaches with 64-bit to the Runway processor bus and 128-bit to the memory, 960 MB/s data rate
- Up to eight Slave Memory Controllers SMCs attach to one MMC on its memory address bus. The SMCs carry the functionality to interface with specific types of DRAM.
- Data Multiplexers DMs attach the 128-bit 60 MHz data bus of the MMC to memory banks. Each two sets of memory connect with two 64-bit 30 MHz buses to the DMs.
- Physical address space of 36-bit for 32 GB main memory
- Memory address bus is shared between all SMCs of a MMC, 39-bit at 60 MHz
- Memory data bus attaches to the DMs and memory
Used in
Dino/Cujo
Dino is the GSC to PCI bridge found in many older PCI PA-RISC workstations. The GSC and PCI buses do not need to be synchronized, simplifying the system design. Dino also implements a small set of I/O functions. Cujo is a Dino bridge for 64-bit PCI.
- GSC bus interface with GSC+ feature, >40 MHz
- PCI bus interface (PCI64 on Cujo), >33 MHz
- Two PS/2 interfaces, RS-232 port
- Mapping register with 8 MB resolution
- Integrated PCI arbitration
- Integrated interrupt register
- Supports both 3.3 V and 5.0 V PCI operation
Used in
- 743i, 745, 744, 748i
- A180, A180C
- C100, C110 C160, C180, C200, C240, C360
- D-Class and R-Class
- J200, J210, J210XC, J280, J282, J2240
- K-Class
- HP Agilent 16600A, 16700A, 16700B, 16702A and 16702B series logic analyzers
References
- Visualize J200, J210 technical reference manual (URL gone)
- Symmetric Multiprocessing Workstations and Servers System-Designed for High Performance and Low Cost (.pdf) William R. Bryg, Kenneth K. Chan, and Nicholas S. Fiduccia (February 1996: Hewlett-Packard Journal)
- A New Memory System Design for Commercial and Technical Computing Products (.pdf) Thomas R. Hotchkiss, Norman D. Marschke, and Richard M. McClosky (Februar 1996: Hewlett-Packard Journal)
- DINO ERS (External Reference Specification) — A GSC-to-PCI Bridge Hewlett-Packard Company (February 1997, Revision 3.0)
- Dino 3.1 (1FC3-0004) Errata Listing Hewlett-Packard Company (September 1997)