Fabrication of PA-RISC Processors

HP designed all of its PA-RISC processors inhouse for two decades – through the VLSI Technology Center (VTC) and Systems & VLSI Technology Operation (SVTO). For more than a decade, HP also manufactured PA-RISC processors in its own facilities (fabs) in Colorado, from TS-1 (1986) in TTL to 64-bit PA-8200 in CMOS (1997). Close to PA-RISC’s Decline, HP switched to Intel fabs for two years and then to IBM in 2001.

PA-RISC Processor manufacturing details
Fabrication Year CPU Die
mm and gates		 FETs Process Details
HP TTL
HP NMOS		 1986—1988 TS-1
NS-1
NS-2		 SRAMs/PALs
8.4×8.4 1.7µ
14.0×14.0  1.5µ		 TTL
115k
183k		 FAST TTL
NMOS-III
NMOS-III		 First CPU, six boards
Eight VLSI support chips
Seven support chips
HP CMOS 1990—1997 PCX
PA-7000
PA-7100
PA-7100LC
PA-7200
PA-7300LC
PA-8000
PA-8200		 1.0µ
14.2×14.2  1.0µ
14.0×14.0  0.8µ
14.2×14.2  0.75µ
14.0×15.0  0.55µ
15.3×16.9  0.5µ
17.7×19.1  0.5µ
17.7×19.6  0.5µ		 196k
577k
850k
900k
1.3M
9.2M
3.8M
4.5M		 CMOS26B
CMOS26B
CMOS26B
CMOS26B
CMOS14A
CMOS14C
CMOS14C
CMOS14C		 PA-RISC 1.0
PA-RISC 1.1, external FPU
on-chip FPU
on-chip MIOC, multimedia

on-chip MIOC/cache, media
PA-RISC 2.0
Intel CMOS 1998—2000 PA-8500
PA-8600		 21.3×22.0  0.25µ
21.3×22.0  0.25µ 		140M
140M		 P856
P856		 Large on-chip cache
IBM SoI 2001—2005 PA-8700
PA-8800
PA-8900		 16.0×19.0  0.18µ
23.6×15.5  0.13µ
23.6×15.5  0.13µ 		186M
300M
317M		 8S2SOI
CMOS 9S
CMOS 9S		 Higher clock
Huge CPUs, dual-core
Final PA-RISC design
Intel CMOS 2001—2006 Merced
Itanium 2		 0.18µ
0.18-0.13µ		 325M
221M		 P858
Px60		 Intel IA64 VLIW, large L3
HP EPIC VLIW

HP was one of the few workstation and server vendors that designed and manufactured almost everything inhouse – from processor architecture, CPU design, fabrication to actual workstation and server design and integration. This also contained HP-designed and build expansion cards and peripherals plus the HP-UX Unix ecosystem.

up

HP TTL

The first PA-RISC processor TS-1, released by HP in 1986, was implemented in TTL. A few years before TS-1, the first PA-RISC in TTL, HP already implemented a complex 32-bit processor in NMOS, the pre-RISC FOCUS CPU.

The TS-1 processor was implemented on six 8.4×11.3″ boards of TTL and was used in the first PA-RISC computers shipped by HP in the 1980s. The six boards used FAST TTL with 25ns/35ns SRAMs/PALs and about 150 ICs each making up the following units:

  1. I-unit Instruction Unit
  2. Register File Board, contains general and control registers
  3. E-unit Execution Unit
  4. TLB translation lookaside buffer with 4096 entries for 2 KB pages
  5. Cache controller with split instruction and data caches of 64 KB each
  6. FPC floating-point coprocessor, taken over from FOCUS

Caches and TLB were off-chip in discrete boards, as was the floating point unit, a separate coprocessor.

HP moved to NMOS fabrication for the next PA-RISC 1.0 processors in the late-1980s, before moving to and staying with CMOS in the 1990s for PA-RISC 1.1 and 2.0.

up

HP NMOS

HP’s ambitious NMOS processors were manufactured inhouse at HP, in its Colorado facilities in Loveland, an unlikely, isolated part of northern Colorado. NMOS processors manufactured in Colorado in the 1980s include FOCUS, for the HP 9000 520 computer, and the second and third PA-RISC processors, NS-1 and NS-2. NMOS and the Loveland facility were used heavily for HP calculators, making Loveland the largest NMOS production facility in the world in the 1970s.

PA-RISC NS-1
HP NS-1, © HP 1987

NS-1 and NS-2 were manufactured in NMOS-III, the third version of HP’s NMOS process that started in 1969—1970 with manufacturing first integrated chips (ICs), based on HP Labs R&D. HP chose NMOS-III for the processors, due to density and speed required for the design, but also because of its proven manufacturability.

The NMOS-III process in NS-1 and NS-2 processors used pure tungsten to connect elements on the chip, a major departure from [previous] IC practice, with 1.7µ drawn channel lengths (0.95µ effective channel lengths). 2.5-µ minimum contacted pitch, and two levels of tungsten metallization.

In comparing its NMOS-based NS-1 and NS-2 PA-RISC processors to the Digital VAX competition, HP claimed HP gained a competitive edge over Digital because the HP-PA systems used lower powered NMOS III chips that rivaled the performance that Digital's VAXes attained with the more expensive and powerhungry ECL (emitter coupled logic) technology.

The NS-1 PA-RISC processor had a 8.4×8.4 mm² die with 115,000 FETs, produced in HP’s NMOS-III 1.5µ process, packaged in a 272-pin ceramic PGA. NS-1 needed eight VLSI support chips (system interface, cache, TLB and FPU) to form the main processing unit.

The NS-2 PA-RISC processor had a 14.0×14.0 mm² die with 183,000 FETs, produced in HP’s NMOS-III 1.5µ process, packaged in a 408-pin PGA. NS-2 needed seven VLSI support chips (system interface, cache, TLB and FPU) to form the main processing unit.

NS-1 and NS-2 were the only and last PA-RISC processors manufactured in NMOS, before HP transitioned PA-RISC manufacturing to CMOS in its Colorado facilities. A few device controllers and I/O chips were still manufactured in NMOS-III for a while, though.

up

HP VLSI CMOS

With the advent of the RISC era of the 90s, HP moved to fabbing its PA-RISC processors from NMOS in CMOS, when it still had rather advanced IC manufacturing facilities inhouse. All PA-RISC processors of the PA-RISC Growth and Maturity periods of the 1990s were manufactured in HP CMOS processes in HP Fort Collins, Colorado facility.

HP developed and used several CMOS processes during that time, before switching fabrication in the late-1990s to external foundries. Processes used in PA-RISC processors were CMOS26B, CMOS14A and CMOS14C, making the jump from 1.0µ over 0.8µ to 0.5µ.

CMOS26B: PCX, PA-7000, PA-7100 and PA-7100C

HP’s CMOS26 or CMOS26B process was used for many popular PA-RISC processors and quite a few chipset and device ICs by HP too. CMOS26B ranged between 1.0µm and 0.75µm, with double metal or triple aluminium layers.

The first PA-RISC processor implemented in CMOS was the PA-RISC 1.0 PCX, released in 1990 and manufactured in HP CMOS26B (or CMOS26). PCX was the last PA-RISC 1.0 processor and formed the processing core of the follow-on PA-7000 (PCX-S) CPU. It still needed external support chips (cache, bus interface) and an external FPU (ECL logic?) and had large external caches, two-way set associative.

PCX was manufactured by HP in 1.0µ double or triple metal CMOS26B with 196,000 FETs, packaged in a 408-pin multilayer PGA.

PA-RISC NS-1
HP PCX-S, © HP 1989

The second PA-RISC processor fabbed in HP CMOS and the first to implement PA-RISC 1.1 was PA-7000, PCX-S, released in 1991 for HP’s Snakes workstations.

After the PCX, the goal for HP was a processor implementation was to allow system designers the flexibility to configure it to support a wide range of price/ performance points to make it compatible with systems ranging from low cost desktop workstations up through midrange multiuser systems.

PA-7000, PCX-S, the first PA-RISC 1.1 processor, had a 14.2×14.2 mm² die with 577,000 transistors (FETs), manufactured in a 1.0µ, three-level alumnium CMOS26 process, packaged in 408-pin ceramic PGA. The MIOC, the system and memory interface (MSBC), was a separate ASIC with 185,000 FETs (part of the ASP chipset) as was the floating-point coprocessor, fabbed by Text Instruments. Caches were external TTL I/O asynchronous SRAM chips, directly interfacing the CPU and FPC.

Due to the aggressive development schedule, HP needed a semiconductor partner with high-performance CMOS floating-point technology [...] to codevelop the PCX-S floating-point coprocessor, in this case Texas Instruments, that manufactured the 64-bit FPC its 0.8µ EPIC-2 process with 640,000 FETs in a 207 PGA.

PA-7100, PCX-T, was the follow-on to the PA-7000, released a year later in 1992 with small but significant improvements. It was the first PA-RISC processor to integrate the floating-point FPU onto a the main die. The overall design of the processor core was kept close to the PA-7000 and modified by HP slightly to scale to higher clock speeds.

PA-7100 processors
PA-7100 modules, © HP 1994

The FPU, external with earlier designs, was redesigned by HP inhouse and moved onto the chip by the design team, taking up about one third of the transistor count, making up the majority of FET increase from PA-7000 to PA-7100. PA-RISC 1.1 PA-7100 processors were fabbed in HP’s 0.8µm triple metal-aluminium CMOS26B processor onto a 14.0×14.0mm die with 800,000 FETs, packaged in a custom 504 pin interstitial ceramic PGA.

Even though many other RISC design moved to on-chip caches for performance reasons, the off-chip caches at the PA-7100 allowed HP to integrate very large, multi-MB caches with its processors.

PA-7150 PCX-TX, was a slightly-tweaked PA-7100 core to allow clock frequencies up to 125 or even 150 MHz in HP 9000 735 and 755 workstations, using supposedly the same CMOS process.

PA-7100LC and LASI
PA-7100LC and LASI dies, © HP Journal 1995

PA-7100LC was the successor to the PA-7100 PA-RISC processor, still implementing 32-bit PA architecture in a highly-integrated package. HP redesigned the core and process slightly, allowing for a second ALU, additional instructions and bus interface on-chip. However, the PA-7100LC, as its PA-7300LC follow-on, was optimized for low cost/performance workstations and not primarily for design.

PA-7100LC was manufactured in 0.75µm triple aluminium CMOS26B, packaged in a 432 pin PGA from Kyocera with 800,000 FETs. MIOC and FPU were integrated on-chip.

Also manufactured in HP’s CMOS26 process was Artist, the integrated graphics adapter of the HP 9000 712 workstation and LASI, the integrated chipset. CMOS26B technology allows the bus interface, macro function unit, and frame buffer controller blocks of the graphics chip to operate at 80 MHz while the three DACs and two color lookup tables of the video block operate at 135 MHz.

Many other HP chipsets and devices were also manufactured for a long time by HP in CMOS26, including the ASP chipsets used in HP 9000 735 and 755

CMOS14A: PA-7200

PA-7200 processors
PA-7200 modules, © HP 1996

HP moved in 1995 from CMOS26 to CMOS14, a new, smaller manufacturing process in 0.55µ, also utilized in the first 64-bit PA-RISC processors later. With this step, HP was the last of the major CPU vendors to move beyond a 0.8-micron manufacturing process, CMOS14A, the variant used in the PA-7200 processor, was co-developed with Analog Devices and was designed for the unusual level of 4.4V.

PA-7200 was the penultimate PA-RISC 1.1 32-bit processor, released in 1995 and closely based on the PA-7100 from 1992. It was designed for enhanced performance in a four-way multiprocessor system without additional interface circuits. This included enhancements to the core and glue for multiprocessing, including adapting the PA-RISC CPU core to the Runway processor bus.

With a short time to market, the entire PA-7200 was designed using the existing CMOS26 technology, and the artwork was then automatically translated to and reverified in the CMOS14 process. It had two ALUs and one FPU (taken over from the PA-7100) on-chip; caches were again off-chip at processor speed SRAMs. It was the last 32-bit PA-RISC 1.1 processor to be designed and manufactured for speed and performance.

PA-7200 was fabricated in 0.55µm triple metal CMOS14A, with a die size of 14×15 mm with 1,300,000 FETs, packaged in an enormous package, 540-pin ceramic PGA. The PA-7200 dissipated 29W at 140 MHz and required a hefty heat sink. They were rumoured to have cost twice as much to manufacture as the PA-7100 – around $280.

CMOS14C: PA-7300LC, PA-8000 and PA-8200

In the span of two years between 1995 and 1996, HP released the last three PA-RISC processors in its own CMOS process – PA-7300LC, PA-8000 and PA-8200 were all fabbed in CMOS14C in HP’s Colorado facilities. HP extended the 0.55µm manufacturing process from the earlier PA-7200, the process, called CMOS-14C, is a 10% gate shrink of HP’s CMOS-14.

PA-7300LC was the last 32-bit PA-RISC 1.1 processor and the first to have large on-chip L1 caches to squeeze out more performance before the move to 64-bit. HP added a very large embedded primary cache, now feasible with the 0.5-µm technology as the CMOS14C process would allow an on-chip cache of reasonable size.

Except for the process shrink from CMOS26 to CMOS14, much of the superscalar integer data path on the PA-7300LC was leveraged from the PA- 7100LC unchanged. Also, many of the cells used in the integer data path wete used in other data path blocks on the chip. Although some of the circuits were reworked for speed improvements, the floating-point unit was also highly leveraged from the PA-7100LC.

The designers kept the PA-7300LC design focus close to its PA-7100LC predecessor – focusing on low cost/performance workstations and not raw performance. The improved CMOS14C process allowed HP’s PA-RISC designers to extend the PA-7100LC core for full two-way superscalarity and integration of the L1 cache – increasing the PA-7100LC’s transistor count tenfold. Besides using much PA-7100LC logical design, the PA-7300LC made use of most of the standard cell libraries were borrowed from the PA-8000 project.

PA-7300LC processors were manufactured in 0.5µm process, 4-layer metal CMOS14C, the die is 15.3mm×16.9mm with 9.2 million FETs, packaged in a low-cost 464-pin ceramic pin-grid array package (CPGA). PA-7300LC were designed to run up to 160 MHz at first, later increased to 180 MHz.

PA-8000 processor
PA-8000 die, © HP Journal 1997

HP designed the 32-bit PA-7300LC and 64-bit PA-8000 in parallel, using the same design and manufacturing process but two separate design teams. The PA-8000 was fabricated using the same IC process technology as the PA-7300LC, but was farther along in the design cycle. The PA-7300LC team was able to use almost the entire PA-8000 core logic library unchanged.

The PA-8000 featured a completely redesigned processing core, moved to 64-bit and did not feature any leveraged circuitry or logic from earlier PA-RISC processor. HP increased the functional units from three (on PA-7200 and PA-7300LC) to ten – four integer, four floating-point, two load-store, and added new multimedia extensions, MAX-2.

PA-8000 was manufactured in HP’s 0.5-micrometer, 3.3-volt CMOS14C process with five metal layers, with the drawn geometries are not very aggressive. The die is 17.68mm×19.1mm in size with 3.8 million FETs, packaged in a 1,085-pin package ceramic LGA. Caches were again single-level off-chip, implemented in SRAMs. PA-8000 were supposed to scale to 250 MHz but were fabbed only up to 180 MHz due to cache SRAM speed.

The PA-8200 was released in 1997, a year after the PA-8000 and designed almost in tandem. Based closely on the PA-8000 core, HP improved the PA-RISC processing logic for performance and time-to-market. The TLB and especially BHT, Branch History Table, were extended due to changed to the prediction algorithm

For the PA-8200, the designers had to stick with this aging process, so they focused on modifying the circuit design to speed critical internal timing paths. HP was able to increase frequency from 180 MHz to 240 MHz (300 MHz in design), as was the cache size (4 MB) and frequency to beyond 200 MHz.

PA-8200 was manufactured in HP’s 0.5-micrometer, 3.3-volt CMOS14C process with five metal layers, the die is 17.7×19.6 with 4.5 million FETs. It scaled up to 300 MHz but was shipped with up to 240 MHz. Caches were again off-chip SRAMs

HP took a big step after the PA-8200 and outsourced its PA-RISC processor fabrication, since HP fabs could not keep up with the rapid advancements in CMOS fabrication. HP moved first to Intel for two CPUs im CMOS and then onward to IBM for three more CPUs in an advanced SoI process.

up

Intel CMOS

— to be extended

up

IBM SoI

— to be extended

up

Intel CMOS

— to be extended

up

Documentation

up