Hitachi PA-RISC Processors

Overview

Hitachi was part of the PRO consortium for PA-RISC and offered both rebadged and their own workstations with HP processors. In parallel, Hitachi also designed their own custom PA-RISC processors, the PA/50 and HARP-1.

Hitachi PA/50L and PA/50M

The Hitachi PA/50 was a family of PA-RISC 1.1 processors designed and manufactured by Hitachi, released in 1993. Two designs were developed: M with around 100 MIPS and L low-cost with around 55 MIPS. Hitachi used them as personal workstation processors and high-end embedded controllers in their own Hitachi workstations.

Thr PA/50 integrated a set of features not available at that time in other PA-RISC processors like on-chip caches, data-prefetching, a power-saving mode and SDRAM support.

PA-RISC version 1.1 32-bit
Built-in, pipelined FPU
Cache 8 KB L1 instruction, 2-way set-associative, 32-byte blocks, on-chip
Cache 4 KB L1 data, 2-way set-associative, 32-byte blocks, copy-back, on-chip
Uncacheable memory (per page)
TLB: 32/64-entry, 2-way set, 4K-page, each +2 additional block entries
BTLB (256 KB-32 MB)
Seven 32-bit shadow registers for fast interrupts
Data-prefetching
Non-blocking cache
Power-saving mode, reducing frequency to 1/8
Support for SDRAM
PA/50L: Up to 33 MHz frequency with 3.3 V core voltage
PA/50M: Up to 60 MHz frequency with 5.0 V core voltage
11.5×12.0 mm² die, 1,280,000 FETs, 0.6µ (micron), 3-layer metal CMOS packaged in a 160-pin plastic QFP package

Used in

Hitachi 3050RX 100C and , 200 workstations

↑ up

Hitachi HARP-1

Hitachi HARP-1 is a PA-RISC version 1.1 compatible CPU from Hitachi, introduced in June 1994. It is apparently a larger and faster version of the PA/50 processor with not much more information available publically. The HARP-1E supposedly included pseudo-vector processing modifications used in Hitachi vector supercomputers. L1 cache was increased to 16 KB/16 KB.

PA-RISC version 1.1 32-bit
Three functional units: two integer ALUs, one floating point unit (FPU) plus two shift-merge units (SMUs)
Six-stage pipeline
Built-in, pipelined FPU
Built-in memory controller Memory Interface Unit, MIU
2-way superscalar
Cache 8 KB L1 instruction, 1-way set-associative, 32-byte blocks, on-chip
Cache 16 KB L1 data, 2-way set-associative, 32-byte blocks, copy-back, on-chip
Cache 512/512 KB L2 instruction/data, off-chip
TLB: 128/128-entry instruction/data, 1-way set
L2 Cache bus: 128-bit data path to L2 caches with ECC
Processor bus: 64-bit data path to main memory and I/O
Up to 150 MHz frequency with 3.3 V core voltage, 17W power dissipation at 120 MHz
16.2×16.5 mm² die, 2,800,000 FETs, 0.5µ, 3-layer aluminium + 1-layer tungsten BiCMOS, packaged in 595-pin PGA

Used in

Hitachi SR2001 supercomputers
Hitachi SR2201 supercomputers (HARP-1E)
Probably others

↑ up

Hitachi HARP-1E

After HARP-1, there was apparently a successor processor presented by Hitachi at HOT CHIPS conference in 1995. It is unclear if that is the HARP-1E and if it was implemented or productized. The concept planned for a high-performance superscalar RISC processor, optimized for large-scale scientific calculations with high-memory troughput and high frequency.

PA-RISC version 1.1 32-bit
Three functional units: two integer ALUs, one floating point unit (FPU) plus two shift-merge units (SMUs)
Six-stage pipeline
2-way superscalar: two instructions issues per cycle, four operations
Vector processing PVP-SW (Pseudo-Vector Processing based on slide-windowed registers)
Cache 16/16 KB L1 instruction/data, on-chip, direct-mapped, 32-byte blocks
Cache 4/4 MB L2 instruction/data, on-chip?, 128-byte lines, ECC
TLB: 256/256-entry instruction/data, direct-mapped
BTLB: 8k-entry 2-way set associative
Branch History Table (BHT) 1024-entry
Up to 150 MHz frequency with 2.5 V core voltage, 13W power dissipation
15.7×15.7 mm² die, 4,500,000 FETs, 0.3µ 4-layer metal CMOS, packaged in 1672-pin PGA

Used in

Not sure

↑ up

Documentation

Chronology of Workstation Computers (1993) Ken Polsson (November 2007. Accessed November 2007)
PROgress (PA-RISC) Newsletter - comp.sys.hp Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (PDF) Hidekazu Terai et al (October 1999: Hitachi Ltd. Accessed January 2008)
PROgress (PA-RISC) Newsletter - comp.sys.hp, Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
HITACHI CLAIMS TO HAVE THE INDUSTRY’s CHEAPEST UNIX WORKSTATION, USING PRECISION ARCHITECTURE..., CBR Online Archive, 28 Oct 1993
October 1993 PROgress Newsletter, USENET post, Google Archive, 11/01/1993
A 120- MHz BiCMOS Superscalar RISC Processor, Shigeya Tanaka et al (IEEE Journal of Solid-State Circuits, vol. 29, no. 4, April 1994)
A 150MHz Superscalar RISC Processor with Pseudo Vector Processing Feature, Hitachi, HOT CHIPS 7 (1995)

↑ up