PA-RISC Processors

Other PA-RISC processors

Several other third-party processor designers implemented PA-RISC processors and solutions both for workstation and server use (Hitachi) but also for embedded systems of the 1990s like set-top boxes, TVs and for device controllers such as printers.

Other PA-RISC processors overview
CPU	ISA	Release	Clock	Cache	Bus	Super scalar	Units	Controllers on-chip
Hitachi PA/50L	PA 1.1 32-bit	1993	33MHz	12KB	?	1-way	1 Integer 1 Floating Point
Hitachi PA/50M	PA 1.1 32-bit	1993	60MHz	12KB	?	1-way	1 Integer 1 Floating Point
Hitachi HARP-1	PA 1.1 32-bit	1994	150MHz	24KB 1MB L2	?	2-way	2 Integer 1 Floating Point (Vector)
Winbond W89K	PA 1.1 32-bit	1994	33/66MHz	4KB	Intel 486	1-way	1 Integer	none?
Winbond W90210 W90215	PA 1.1 32-bit	1997	33/66MHz	12KB	Intel 486	1-way	1 Integer MAX-1	DRAM DMA PCI I/O
Winbond W90220 W90221	PA 1.1 32-bit	1999	150MHz	8KB	Intel 486	1-way	1 Integer 1 MAC(DSP) MAX-1	DRAM DMA PCI IDE I/O VGA (W90221) TV (W90221)
Oki OP32	PA 1.1 32-bit	1994	33MHz	?	?	1-way	1 Integer	DRAM DMA
Amiga Hombre	PA 1.1 32-bit	1995	125MHz	?	64-bit	1-way	1 Integer	Memory DMA PCI I/O VGA audio Copper Blitter

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Hitachi PA/50L and PA/50M processors

The Hitachi PA/50 was a family of PA-RISC 1.1 processors designed and manufactured by Hitachi, released in 1993. Two designs were developed: M, with around 100 MIPS, and L, low-cost, with around 55 MIPS. They were used as personal workstation processors and high-end embedded controllers and integrated a set of features previously not available at that time in other PA-RISC processors like on-chip caches, data-prefetching, a power-saving mode and SDRAM support.

PA-RISC version 1.1 32-bit
Built-in, pipelined FPU
L1 I: 8 KB, 2-way set-associative, 32-byte blocks
L1 D: 4 KB, 2-way set-associative, 32-byte blocks, copy-back
L1 caches are on-chip
Uncacheable memory (per page)
TLB: I/D 32/64-entry, 2-way set, 4K-page, each +2 additional block entries
BTLB (256 KB-32 MB)
Seven 32-bit shadow registers for fast interrupts
Data-prefetching
Non-blocking cache
Power-saving mode, reducing frequency to 1/8
Support for SDRAM
PA/50L: Up to 33 MHz frequency with 3.3 V core voltage
PA/50M: Up to 60 MHz frequency with 5.0 V core voltage
11.5×12.0 mm² die, 1,280,000 FETs, 0.6µ (micron), 3-layer metal CMOS packaged in a 160-pin plastic QFP package

Used in

Hitachi 3050RX 100C, 200 workstations

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Hitachi HARP-1 processor

The Hitachi HARP-1 is a PA-RISC version 1.1 compatible CPU from Hitachi, introduced in June 1994. It is apparently a larger and faster version of the PA/50 processor, however . not much information is available on either processor.

The HARP-1E variant supposedly includes (pseudo) vector processing modifications/add-ons and was used in Hitachi vector/supercomputers. It seems the L1 cache was increased to 16 KB/16 KB instruction/data.

PA-RISC version 1.1 32-bit
Three functional units: two integer ALUs and one floating point unit and two shift-merge units
Six-stage pipeline
Built-in, pipelined FPU
Built-in memory controller Memory Interface Unit, MIU
2-way superscalar
L1 I cache: 8 KB, 1-way set-associative, 32-byte blocks
L1 D cache: 16 KB, 2-way set-associative, 32-byte blocks, copy-back
L1 caches are on-chip
L2 I/D 512/512 KB, off-chip
TLB: I/D 128/128-entry, 1-way set
Some say a second level TLB was included
L2 Cache bus: 128-bit data path to L2 caches with ECC
Processor bus: 64-bit data path to main memory and I/O
Up to 150 MHz frequency with 3.3 V core voltage, 17W power dissipation at 120 MHz
16.2×16.5 mm² die, 2,800,000 FETs, 0.5µ 3-layer aluminium + 1-layer tungsten BiCMOS, packaged in 595-pin PGA

Used in

Hitachi SR2201 supercomputer (HARP-1E)
Probably others

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Winbond W89K processor

The Winbond W89K is an embedded 32-bit PA-RISC controller chip, pin-compatible with the then-popular Intel 80486DX, introduced in Spring 1994. It could be used as a drop-in replacement in mid-1990s PCs together with Winbond BIOS replacement chips. Rationale was to allow hardware developers utilize existing 486DX mainboards and components for a shorter product development process. The W89K is a level 0 PA-RISC 1.1 implementation: a 32-bit PA-RISC processor without virtual addressing.

PA-RISC version 1.1 32-bit
Level 0 implementation, no virtual addressing: no MMU
Five-stage pipeline
One functional unit: one 32-bit integer ALU
2 KB/2 KB I/D on-chip L1 caches
80486 Intel bus interface
33 MHz and 66 MHz clock speeds were available, with the latter apparently having been achieved with a clock-doubling also used in the Intel’s 80486DX/2
On-chip JTAG support
14.3×14.3 mm² die, 1,100,000 FETs, 0.8µ, 3-layer metal CMOS

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Winbond W90210/215 processor

Shortly after the W89K embedded controllers Winbond introduced more sophisticated PA-RISC processors in Fall 1997 with the W90K line of embedded controllers. The W90210F still was 32-bit PA-RISC 1.1 but integrated many external I/O components on the chip — DRAM and DMA controllers, a PCI bridge and various I/O ports. As its predecessor, the W90210F was a level 0 PA-RISC 1.1 implementation without virtual addressing. It was apparently used in various Internet appliances: set-top boxes, TV sets, DVD players, PDAs, VoIP devices, and for industrial automation. The W90215 is identical to the W90210 but did not include license rights for the embedded operating system and was thus cheaper.

PA-RISC version 1.1 32-bit
Level 0 implementation no virtual addressing: no MMU
Five-stage pipeline
One functional unit: one 32-bit integer ALU
L1 I cache: 4 KB, direct mapped, 32-byte blocks, 256 entries
L1 D cache: 8 KB, 2-way set-associative, 32-byte blocks, 2×64 entries, write-back
MAX-1 multimedia extensions for multimedia applications, like MPEG decoding
80486 Intel bus interface
DRAM controller
ROM/FLASH interface
DMA controller 2-channel 8-bit
PCI bridge
Two serial ports
Parallel port
33 MHz and 66 MHz clock speeds
208-pin PQF package

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Winbond W90220 and W90221 processors

The W90220F is, as its predecessor W90210, a 32-bit PA-RISC 1.1 design without MMU but integrated many external I/O components on the chip — DRAM and DMA controllers, PCI bridge, IDE channels, I/O ports and, on the W90221, a graphics/TV chip. Released in Spring 1999, it had the same target systems of set-top boxes and internet appliances. The sucessor W90221 is apparently similar, with higher clock speed, integrated (S)VGA and TV controller

PA-RISC version 1.1 32-bit
Level 0 implementation, no virtual addressing: no MMU
Six-stage pipeline
Two functional units: one 32-bit integer ALU and one 32-bit multiply-accumulate MAC module, for DSP purposes, can be used as two 16-bit modules too
L1 I cache: 4 KB, direct mapped, 32-byte blocks, 256 entries
L1 D cache: 4 KB, 4-way set-associative, write-back or write-through
MAX-1 multimedia extensions for multimedia applications, like MPEG decoding
80486 Intel bus interface
Hardware dynamic branch prediction
256-entry branch-target-buffer BTAC
Memory controller supports DRAM, EDO-DRAM and SRAM; W90221 additionally SDRAM
ROM/FLASH interface
DMA controller 2-channel 8-bit
IDE I/O controller four 16-bit channels
W90221: VGA and TV controller W9971
PCI bridge
Two serial ports
Parallel port
Serial ICE port
Up to 150 MHz clock speed at 3.3 V/5 V I/O and 3.3 V core
W90221: 133 MHz clock speed with apparently 3.3 V at both I/O and core
0.35µ single-poly-triple-metal CMOS
208-pin PQF package

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Oki OP32 processor

Oki Semiconductor OP32/50N was introduced in 1994 as an embedded controller, based on a 32-bit PA-RISC design with integrated DRAM and DMA controllers. The chip was targeted at laser printers, Fax machines, X-Terminals and the Telecom and Automotive markets.

PA-RISC version 1.1 32-bit
33 MHz frequency
14.3×14.3 mm² die, 1,100,000 FETs, 0.8µ, 3-layer metal CMOS

Amiga Hombre processor

Between 1992 and 1994, Commodore designed a new graphics chipset to power Amiga computers based on HP PA-RISC, called Hombre. The development effort apparently included HP and was based on a PA-RISC core to be available for 1995 production for a CD-based Game Machine, cable TV, MPEG and as a PCI-based graphics accelerator. The Hombre processor design was to be implemented in two chips:

CPU chip (Nathaniel) with 32-bit PA-RISC core: RISC integer core based on PA-7150 at 125MHz, DMA interface, audio and CD interfaces, system, display and PCI buses
Video chip (Natalie) with graphics functions and buses
Both were targeted for 0.6µ, 3-level metal CMOS in 3.3 V in 304-PQFP
50MHz system bus, 64-bit wide

The CPU core was 32-bit PA-RISC 1.1, Integer-only with a 5-stage pipeline and 64-bit datapath

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References

Chronology of Workstation Computers (1993) Ken Polsson (November 2007. Accessed November 2007)
PROgress (PA-RISC) Newsletter - comp.sys.hp Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (PDF) Hidekazu Terai et al (October 1999: Hitachi Ltd. Accessed January 2008)
PROgress (PA-RISC) Newsletter - comp.sys.hp, Candace Doyle (October 1993: Precision Risc Organization. Accessed December 2007)
Winbond, Varian sign deal for thin-film IC process, Terho Uimonen (April 1994: Electronic News. Accessed January 2008 at findarticles.com)
PA-RISC in a PC box (was: Re: HP's vision of a low-end 3000) comp.sys.hp.mpe, Stan Sieler (Februar 1996. Accessed December 2007)
HITACHI CLAIMS TO HAVE THE INDUSTRY’s CHEAPEST UNIX WORKSTATION, USING PRECISION ARCHITECTURE..., CBR Online Archive, 28 Oct 1993
October 1993 PROgress Newsletter, USENET post, Google Archive, 11/01/1993
A 120- MHz BiCMOS Superscalar RISC Processor, Shigeya Tanaka et al (IEEE Journal of Solid-State Circuits, vol. 29, no. 4, April 1994)
W90210F PA-RISC Embedded Controller (.pdf) sWinbond Electronics Corp. (October 1997. Accessed January 2008)
W90220F PA-RISC Embedded Controller (.pdf) Winbond Electronics Corp. (March 1999. Accessed January 2008)
Hombre - The last Commodore custom chipset, Amiga History Guide
CBMs Plans for the RISC-Chipset, Dave Haynie 1995

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