PA-7000 (PCX-S) processor
The PA-7000, or PCX-S, was a 32-bit processor with PA-RISC 1.1 architecture, introduced in 1991. It had a MMU for virtual memory management. It was first used in the HP 9000 700 series workstations and later in some of the HP 9000 800 Nova servers. The PA-7000 was a multi-chip implementation fabricated in HP’s own CMOS26B process with an external FPU.
After previous PA-RISC 1.0 processors from the 1980s were mostly geared towards (expensive) transaction processing and multi-user environments, the PA-7000 was designed to extend PA-RISC
down to low cost desktop workstation systems.
The PA-7000 design process facilitated use of existing technologies, first extension to the PA-RISC architecture and a collaboration with an external silicon vendor (Texas Instruments) for the FPU.
Graphics requirements were integrated into the design process of the PA-7000 processor, memory and system buses.
- PA-RISC version 1.1a, 32-bit architecture
- Two main functional units implemented in two VLSI chips: the integer ALU and external FPU
- The floating point unit was co-developed with Texas Instruments
- Five-stage pipeline
- TLB: 192 entries, BTLB: 8 entries
- Cache 256 KB instruction and 256 KB data L1 off-chip implemented in SRAMs
- Cache data rate is 264 MB/s for instruction and 528 MB/s for data caches at 66 MHz clock
- Memory and I/O controller (MIOC) is external
- PBus processor bus, 32-bit, from processor to the Memory and I/O Controller (MIOC) for up to 265 MB/s
- Up to to 66 MHz clock speed with 5.0 V core voltage
- 14.2×14.2 mm2 die, 577,000 FETs, 1.0µ, 2-layer CMOS26B in 408-pin CPGA
- External FPU fabbed in 13.0×13.0 mm2 die, 640,000 FETs, 0.8µ, TI EPIC-2 in 207-pin CPGA
- HP 9000 705, 710, 720, 730, 750 workstations
- HP 9000 F10, F20, F30, G30, G40, H20, H30, H40, I30, I40 servers
- Mitsubishi ME/R7200, ME/S7200, ME/R7300, ME/S7300, ME/R7500, ME/S7500 workstations
- CMOS PA-RISC processor for a new family of workstations, M. Forsyth et al, COMPCON Spring '91 Digest of Papers, 1991
- Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)
- Midrange PA-RISC Workstations with Price/Performance Leadership (.pdf) pp. 6-11 Andrew J. DeBaets and Kathleen M. Wheeler (August 1992: Hewlett-Packard Journal)
- VLSI Circuits for Low-End and Midrange PA-RISC Computers (.pdf) pp. 12-22 Craig A. Gleason (August 1992: Hewlett-Packard Journal)