PA-RISC information - since 1999

PA-7000 PA-RISC Processor

Overview

PA-7000 (PCX-S) is a 32-bit processor with PA-RISC 1.1 architecture, introduced by HP in 1991. It integrated a MMU for virtual memory management, a first for PA-RISC. PA-7000 were designed for and first used in HP 9000 700 workstations, and only later in some HP 9000 800 servers. The HP processor was a multi-chip implementation fabricated in HP’s own CMOS26B process with an external FPU (TI EPIC-2).

PA-RISC PA-7000 die
PA-7000 die, Thomas Schanz CC BY-SA 4.0

After PA-RISC 1.0 processors from the 1980s were mostly geared towards transaction processing and multi-user environments, the PA-7000 was designed to extend PA-RISC down to low cost desktop workstation systems. The PA-7000 design process used existing technologies but implemented the first extension to PA-RISC architecture and collaborated with Texas Instruments for the FPU, a first for HP.

PA-7000 leveraged previous PCX PA-RISC design for the computing core, extending it to PA-RISC 1.1.

Graphics requirements were integrated into the design process of the PA-7000 processor, memory and system buses, as PA-RISC computers were used frequently for 2D/3D design in the 90s. Performance features for graphics support included: Block TLB entry for frame buffer, several FP and graphics instructions, data cache prefetch, and register and load/store features.

Processor details

Functional units

The PA-7000 is a 32-bit PA-RISC processor, implementing version 1.1a of the PA-RISC architecture. It is single-processor only and one-way scalar.

There are two functional units in two VLSI chips in the PA-7000: one Integer ALU and one external Floating Point unit (FPU or FPC), co-developed with Texas Instruments. The PA-7000 CPU has a five-stage pipeline.

PA-7000 have a Translation Lookaside Buffer (TLB) with 192 entries (instruction and data), fully associative for virtual-to-physical memory address translations and a Block Translation Lookaside Buffer (BTLB) with 8 entries for virtual-to-physical page translations.

Cache and memory

PA-7000 use off-chip L1 caches, quite large for the time: up to 256 KB instruction and 256 KB data caches in TTL SRAMs, and no L2 caches. Cache data rate is 264 MB/s for instruction (32-bit) and 528 MB/s for data caches (64-bit) at 66 MHz clock.

Memory and I/O controller (MIOC) for accessing the memory and main buses is external on PA-7000. Address space 32-bit physical, 48-bit virtual.

Speed and buses

PA-7000 processors were fabbed with up to 66 MHz clock speed, on 5.0 V core voltage. They attach to the PBus processor bus, with 32-bit from processor to Memory and I/O Controller (MIOC) for up to 265 MB/s.

Physical

Fabricated by HP, PA-7000 have a 14.2×14.2 mm² die with 577,000 transistors (FETs) in a 1.0µ, 2-layer CMOS26B process and packaged in 408-pin CPGA. The external FPU was fabbed as a 13.0×13.0 mm² die with 640,000 transistors (FETs) in 0.8µ, Texas Instruments EPIC-2 process, packaged in 207-pin CPGA.

The CPU draws 8W power at 66 MHz.

Performance

HP PA-7000 PA-RISC processors (1991) were average RISC performers of the early 1990s with roughly the same performance as MIPS R3000A (1992), Motorola 88100 (1988) and SPARC (1991 implementations) but slightly slower than IBM POWER1 (1990), Sun SuperSPARC (1992) and MIPS R4000 (1991) at similar clocks.

Compared to personal computers of that era, PA-7000 were faster than Intel 486DX2 (1992) and level with later Pentium P5 (1993) at the same frequencies, but significantly stronger in floating point than both.

Used in

Documentation

  1. CMOS PA-RISC processor for a new family of workstations, M. Forsyth et al, COMPCON Spring '91 Digest of Papers, 1991
  2. Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC André Seznec and Thierry Lafage (INRIA: June 1997)
  3. Hewlett-Packard Journal August 1992 archive.org
    • Midrange PA-RISC Workstations with Price/Performance Leadership, page 6 (Andrew J. DeBaets and Kathleen M. Wheeler)
    • VLSI Circuits for Low-End and Midrange PA-RISC Computers, page 12 (Craig A. Gleason et al.)
  4. PA-RISC Processor for Snakes Workstation, Charles Kohlhardt, (1991: Hewlett Packard. Proceedings of IEEE Hot Chips III) archive.org

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