PA-RISC Processors

PA-7100/PA-7150 (PCX-T) processor

Overview

The PA-7100 was the first PA-RISC processor to integrate the Integer ALU and FPU on a single die. It was introduced in 1992, with the enhanced PA-7150 in 1994. The design of the integer units is close to the PA-7000 but modified to scale to higher clock speeds. The previously external FPU was a new design and moved on chip, taking about one third of the transistor count. The link between the PA-7100 and its instruction cache was doubled in width compared to the PA-7000. The PA-7100 is a superscalar processor that is able to issue two separate instructions at a time. It was used in a large range of 1990s HP 9000 workstations and servers.

Multi-processor systems could be designed with two astrategies: either two PA-7100s attach to a shared PBus and one Viper Memory and I/O Controller, or each PA-7100 is attached to its own MIOC, which in turn is attached to a shared memory and I/O bus with the other PA-7100/MIOCs.

The PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up to 125 MHz.

Details

PA-RISC version 1.1b, 32-bit architecture, multi-processor capable, 2-way superscalar
Two functional units: 1 integer ALUs, 1 FPU
Five-stage pipeline
3-instruction queue
TLB: 120-entry fully associative; BTLB: 16-entry
Cache up to 1 MB instruction and 2 MB data L1, in asynchronous standard SRAMs
CPU, FPU, MMU and cache controller on one chip, memory and I/O controller Viper MIOC, off-chip
PBus processor bus, 32-bit, from processor to the Memory and I/O Controller MIOC
Up to to 100 MHz, 125 MHz on the PA-7150, clock speed with 5.0 V core voltage
14.0×14.0 mm² die, 850,000 FETs, 0.8µ, 3-layer metal CMOS26B in a 504-pin ceramic PGA, 30W power at 100 MHz

Used in

HP 9000 715, 725, 735, 755, 742i, 745i, 747i workstations
HP 9000 G50, G60, G70, H50, H60, H70, I50, I60, I70 servers
HP 9000 T500, T520 mainframes
Convex SPP1000/CD, SPP1000/XA mainframes
Hitachi 3050RX 220, 230, 310S, 320, 330, 430, 440, 9000V V735/125, VT500 workstations
Stratus Continuum 610S, 610, 615S, 615, 620, 625, 1220, 1225, 1245 mainframes

References

A 200 MFLOP HP PA-RISC Processor (.pdf) W. Jaffe, B. Miller, J. Yetter (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV)
Multiprocessor Features in a PA-RISC Processor Interface Chip (.pdf) T. Alexander et al (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV)
Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997)

↑ up