PA-RISC information - since 1999

PA-7100 PA-RISC Processor

Overview

PA-7100 is a 32-bit PA-RISC processors, released by HP in 1992. It was the first PA-RISC processor to integrate the integer ALU and floating-point FPU on a single die. The design of the integer units is close to the PA-7000 but modified to scale to higher clock speeds.

PA-7100 die
PA-7100 die, © HP

The previously external FPU was a new HP design and moved by the design team on chip, taking up about one third of the transistor count. The link between the PA-7100 and its instruction cache was doubled in width compared to the PA-7000.

PA-7100 is the first superscalar PA-RISC processor and can issue two separate instructions at a time.

PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up to 125 MHz. Both were a mainstay in PA-RISC growth in the Unix market of the early-1990s with HP 9000 computers.

Processor details

Functional units

The PA-7100 is a 32-bit PA-RISC processor, implementing version 1.1b of the PA-RISC architecture. It is multi-processor capable (SMP) and two-way superscalar, so it can decode, dispatch and execute two instructions per cycle (one CPU, one FPU).

There are two integrated functional units in the PA-7100: one Integer ALU and one Floating Point unit (FPU). The PA-7100 CPU has a five-stage pipeline.

PA-7100 have a three instruction queue and Translation Lookaside Buffer (TLB) with 120 entries, fully associative for virtual-to-physical memory address translations, smaller than on the PA-7000 processor. They also have a Block Translation Lookaside Buffer (BTLB) with 16 entries for virtual-to-physical page translations.

Cache and memory

PA-7100 have only off-chip L1 caches of up to 1 MB instruction and 2 MB data caches, which was unusually large for the time. Cache is implemented in asynchronous standard SRAMs (9ns at 100 MHz), and there is no L2 cache. Cache controller is on-chip, cache access is 64-bit wide.

Memory and I/O controller (HP Viper) to access the memory and main buses is external and off-chip on PA-7100. Address space 32-bit physical, 48-bit virtual (segmented).

Speed and buses

PA-7100 processors were fabbed with up to 100 MHz, PA-7150 up to 125 MHz clock speed, on 5.0 V core voltage. They attach to the PBus processor bus with 32-bit from processor to Memory and I/O Controller (MIOC).

Multi-processor systems could be designed with two strategies: either two PA-7100s attach to a shared PBus and one Viper Memory and I/O Controller (low cost 2-way MP), or each PA-7100 is attached to its own MIOC, which in turn is attached to a shared memory and I/O bus with the other PA-7100/MIOCs.

Physical

Fabricated by HP, PA-7100 have a 14.0×14.0 mm² die with 850,000 transistors (FETs), fabbed in a 0.8µ, 3-layer HP CMOS26B (metal aluminium) process and packaged in 504-pin ceramic PGA. They draw 30W power at 100 MHz (or 20W in earlier sources).

Performance

HP PA-7100 PA-RISC processors were rather fast microprocessors for their time in 1992, on par with their RISC competition and beating even newer processors in floating point. At the same clock, PA-7100 were almost level with Pentium P54C (1994) and MIPS R4400SC (1992) but significantly faster in floating point, SPEC95.

They were significantly (almost twice) faster than DEC Alpha 21064 (1992) at 100 MHz, slightly faster than IBM PowerPC 604 (1994) but slower than higher-clocked Intel Pentium Pro (1995).

Used in

PA-7100 processors were used in the majority of early/mid-1990s HP 9000 workstations and servers, mostly for technical computing.

Documentation

  1. A 200 MFLOP HP PA-RISC Processor, W. Jaffe, B. Miller, J. Yetter (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV) archive.org
  2. Multiprocessor Features in a PA-RISC Processor Interface Chip, T. Alexander et al (1992: Hewlett Packard. Proceedings of IEEE Hot Chips IV) archive.org
  3. Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC (PDF) André Seznec and Thierry Lafage (INRIA: June 1997) hal
  4. PA-7150 PA-RISC Processor (Hewlett Packard: April 1997) archive.org

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