PA-7100LC PA-RISC Processor

PA-7100LC is a 32-bit PA-RISC processor introduced by HP in 1994, designed as a single-chip solution for low-cost systems (LC) with the performance of comparable workstations and servers. The CPU core of the PA-7100LC is close to the earlier 32-bit PA-7100 RISC processor, but integrated FPU, memory controller and first-level cache onto a single chip with main system bus attachment.

PA-RISC PA-7100LC die
PA-7000 die, Thomas Schanz CC BY-SA 4.0

HP added support for bi-endian byte ordering for the first time to PA-RISC with the PA-7100LC, ostensibly for supporting a wider range of non-Unix operating systems, like Windows NT and others.

PA-7100LC processors used HP MAX-1 multimedia extensions for 1990s multimedia applications like MPEG audio and video decoding, as one of the first architectures and processor to do so.

PA-7100LC processor were successfully used by HP as integrated 32-bit RISC CPUs in a large range of lower-cost HP Unix workstations in the mid-1990s. The successor of the PA-7100LC is the similar PA-7300LC processor, much improved and released two years later.

Processor details

Functional units

PA-7100LC implements 32-bit PA-RISC version 1.1c, it is single-processor only and two-way superscalar, thus can decode, dispatch and execute multiple instructions per cycle. Only the first ALU can handle loads, stores and shifts which can only be paired with simple math operations, like integer addition or multiplication.

There are three integrated functional units in the PA-7100LC: two Integer ALUs and one Floating Point unit (FPU) plus MAX-1 multimedia extensions for multimedia applications. The PA-7100LC CPU has a five-stage pipeline.

PA-7100LC have a three instruction queue and Hardware static branch prediction.

The Translation Lookaside Buffer (TLB) has 64 entries, is fully associative, translates virtual-to-physical memory addresses, the Block Translation Lookaside Buffer (BTLB) with 8 entries translates pages (BATC, Block Address Translation Cache).

Cache and memory

PA-7100LC have an on-chip L1 cache of 1 KB on-chip for instructions, prefetched from the off-chip cache. Main cache is off-chip, a combined L1 cache up to 2 MB direct mapped, asynchronous SRAMs. The memory and I/O controller (MIOC) is integrated in PA-7100LC onto the die, for direct DRAM memory and cache interface.

The PA-7100LC supports both little-endian and big-endian ordering for more operating system options, a PA-RISC first. It supports 48-bit virtual addresses and up to 4 GB of physical memory, with non-cached memory pages as another first.

Speed and buses

PA-7100LC processors were fabbed with up to 100 MHz clock speed. They directly attach to the GSC main system bus with 32-bit from processor to graphics I/O devices. Memory and caches buses are 64-bit, controlled by the on-chip MIOC, with up 480 to 600 MB/s datarate, depending on clock.

Physical

Fabricated by HP, PA-7100 had a 14.2×14.2 mm² die with 900,000 transistors (FETs), fabbed in a 0.75µ, 3-layer HP aluminium process packaged in a 432-pin PGA.

Performance

HP PA-7100LC PA-RISC were pretty fast low-cost microprocessors in 1994, on par with RISC and PC competition of their time. At the same clock, PA-7100LC were in the ballpark of IBM PowerPC 604 (1994) and beat Pentium P54C (1994) and MIPS R4400SC (1992) in SPEC92 scores. They were much stronger in floating point.

As MPR put it, PA-7100LC were significantly faster than the PowerPC 601 and dramatically faster than the TI microSPARC, and had far better FP performance than Sun’s microSPARC II and outran the fastest SuperSPARC chip in SPEC92 scores.

Used in

PA-7100LC processors were used in the mainstay of more affordable HP 9000 Unix workstations of the mid-1990s and a few serves and industrial control systems.

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Documentation

  1. PA7100LC ERS (External Reference Specification), Hewlett-Packard Company (PDF, 1999)
  2. The PA 7100LC Microprocessor: A Case Study of IC Design Decisions in a Competitive Environment, Mick Bass et al (PDF, HP Journal 4/95) archive.org
  3. Design methodologies for the PA 7100LC microprocessor, Mick Bass et al (PDF, HP Journal 4/95) archive.org
  4. New PA-RISC Processor Decodes MPEG Video, Microprocessor Report, Volume 8, Issue 1 Article Reprint archive.org
  5. Low-End PA7100LC Adds Dual Integer ALUs, Microprocessor Report, Vol. 6, No. 15, November 18, 1992
  6. Most Significant Bits, Microprocessor Report, Vol. 8, No. 7, May 30, 1994

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