PA-RISC information - since 1999

PA-7200 PA-RISC Processor

Overview

PA-7200 is a 32-bit PA-RISC processor, released by HP in early 1995. It completely revised the PA-7100 processor core, leveraging only the FPU. As two-way superscalar processor, PA-7200 can dispatch and execute two separate instructions at a time to its functional units. In contrast to PA-7100, the newer PA-7200 has two integer ALUs and can execute two integer operations simultaneously.

PA-7200 die
PA-7200 die, © HP

Other changes in the PA-7200 include a redesigned cache which retained the general PA-RISC cache layout with large off-chip L1 caches at processor clock, but changed some of the architecture. PA-7200 use the 64-bit Runway processor bus, carried on to later 64-bit PA-8000 processors.

HP targeted PA-7200 processors towards high-performance general-purpose applications, but designed them also for specialized applications with large working sets which could take advantage of the high-bandwidth bus interface. It was a pretty fast mid-1990s RISC microprocessor.

PA-7200 were expensive to fabricate and were used in only few 32-bit HP 9000 workstations in the mid-1990s before the 64-bit PA-8000 was introduced a year later.

Processor details

Functional units

The PA-7200 is a 32-bit PA-RISC processor and implements version 1.1d of PA-RISC architecture. It is multi-processor capable (SMP) and two-way superscalar, so it can decode, dispatch and execute multiple instructions per cycle.

There are three integrated functional units in the PA-7200: two Integer ALUs and one Floating Point unit (FPU). The PA-7200 CPU has a five-stage pipeline and a three instruction queue and Hardware static branch prediction.

The Translation Lookaside Buffer (TLB) with 120 entries, fully associative, translates virtual-to-physical memory addresses, the Block Translation Lookaside Buffer (BTLB) with 16 entries translates pages (BATC, Block Address Translation Cache).

Cache and memory

PA-7200 have, in the PA-RISC tradition, large off-chip caches at processor speed. There is a 2 KB on-chip assist on-chip cache, fully associative, holds 64 32-Byte cache lines. Main L1 cache is up to 1 MB instruction and 2 MB data, off-chip in asynchronous SRAMs with one cycle latency. There is no L2 cache.

Memory and I/O controller (MIOC) for accessing the memory and main buses is external and off-chip on PA-7200.

The PA-7200 is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-7200 processors were fabbed with up to 140 MHz clock speed at 4.4 V core and 3.3 V I/O voltage. They attach to the Runway system interface, 64-bit, 120 MHz, 960 MB/s peak bandwidth.

For multiprocessing, PA-7200 have a glueless interface for up to four CPUs in SMP on same Runway processor bus.

Physical

Fabricated by HP, PA-7200 were a 14.0×15.0 mm² die with 1,300,000 transistors (FETs), fabbed in a 0.55µ, 3-layer HP CMOS14A process and packaged in 540-pin ceramic PGA. They draw 29W power at 140 MHz.

Performance

HP PA-7200 PA-RISC were very strong microprocessors for 1995, usually above their RISC competition in technical computing. At the same clock, PA-7200 were much faster than IBM PowerPC 604 (1994), Pentium P54C (1994) and MIPS R5000 (1996), with almost twice the performance in floating point.

PA-7200 were almost equal to higher-clocker Pentium Pro (1995) and UltraSPARC (1995) and not far from Digital Alpha 21164 (1996) at significantly higher clocks.

Used in

PA-7200 processors were used in a few mid-1990s HP 9000 technical workstations, before HP switched to 64-bit and Visualize branding, plus a few servers.

Documentation

  1. Design of the HP PA 7200 CPU (.pdf) Kenneth K. Chan et al (February 1996: Hewlett-Packard Journal) (mirror: Design of the HP PA 7200 CPU)
  2. Verification, Characterization, and Debugging of the HP PA 7200 Processor (.pdf) Thomas B. Alexander et al (February 1996: Hewlett-Packard Journal)
  3. A Different Kind of RISC Dick Pountain (August 1994: BYTE Journal)
  4. Interview with David Fotland, September/October 2008
  5. PA-7200 Enables Inexpensive MP Systems, Microprocessor Report, Volume 8, Issue 3 Article Reprint archive.org

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