PA-RISC Processors

PA-7200 (PCX-T') processor

Overview

The PA-7200 completely revised the PA-7100 processor core, leveraging only the FPU in its release in early 1995. Being a two-way superscalar processor, the PA-7200 can dispatch and execute two separate instructions at a time to its functional units.

In contrast to the PA-7100 it has two separate integer ALUs and thus can execute two ALU integer operations simultaneously. Other changes include a redesigned cache architecture — while retaining the general cache layout with large off-chip L1 caches at CPU clock speed — and use of the Runway processor bus, carried on to later PA-8x00 processors. The PA-7200 was targeted towards high-performance general-purpose applications, but also on specialized applications with large working sets which could take advantage of the high-bandwidth bus interface.

Details

PA-RISC version 1.1d, 32-bit architecture, multi-processor capable, 2-way superscalar
Three functional units: 2 integer ALUs, 1 FPU
Five-stage pipeline
3-instruction queue
Hardware static branch prediction
TLB: 120-entry fully associative; BTLB: 16-entry
Cache 2 KB on-chip assist cache, fully associative, holds 64 32-Byte cache lines
Cache up to 1 MB instruction and 2 MB L1 data asynchronous SRAMs with one cycle latency
FPU, MMU, cache controller integrated on die, memory and I/O controller separate and off-chip
Bi-endian support
Runway system interface, 64-bit, 120 MHz, 960 MB/s peak bandwidth
Glueless interface to the Runway system bus for up to four-way SMP, four CPUs on same Runway processor bus
Up to 140 MHz clock speed with 4.4 V core and 3.3 V I/O voltage
14.0×15.0 mm² die, 1,300,000 FETs, 0.55µ, 3-layer metal CMOS14A in a 540-pin ceramic PGA, 29W power at 140 MHz

Used in

HP 9000 C100, C110 workstations
HP 9000 D250, D260, D350, D360 servers
HP 9000 J200, J210 workstations
HP 9000 K100, K200, K210, K220, K400, K410, K420 servers
Convex SPP1200/CD, SPP1200/XA, SPP1600/CD, SPP1600/XA mainframes
Hitachi 9000V VQ200, VQ210, VR100, VR200, VR400 servers

References

Design of the HP PA 7200 CPU (.pdf) Kenneth K. Chan et al (February 1996: Hewlett-Packard Journal) (mirror: Design of the HP PA 7200 CPU)
Verification, Characterization, and Debugging of the HP PA 7200 Processor (.pdf) Thomas B. Alexander et al (February 1996: Hewlett-Packard Journal)
A Different Kind of RISC Dick Pountain (August 1994: BYTE Journal)
Interview with David Fotland, September/October 2008

↑ up