PA-RISC Processors
PA-7300LC (PCX-L2) processor
Overview
The PA-7300LC is an integrated, low-cost
PA-RISC 32-bit processor, released in mid-1996 and used in many mid- to late 1990s integrated HP 9000 workstations.
PA-7300LC was a close successor to the earlier, also highly-integrated PA-7100LC CPU,
it has several enhancements:
- Large on-chip L1 caches, in contrast to the small L1 on-chip
assist
caches of the PA-7100LC and PA-7200 - Integrated L2 cache controller in the on-chip Memory and I/O Controller (MIOC)
- Improved bus interface with faster GSC+ bus variant for up to 160MB/s
- Faster memory interface
The contemporary process technologies made it finally possible for HP to include a large L1 cache on the CPU die, breaking a long-standing HP tradition of large and off-chip L1 caches.
The PA-7300LC was the final 32-bit, PA-RISC version 1.1 processor after the PA-7200. HP 9000 workstations and servers from then on used HP 64-bit PA-RISC 2.0 processors, such as the PA-8000, being introduced in the same timeframe.
HP used the PA-7300LC processor to close the gap on lower price-point workstations at the bottom of its product lineup like A180 servers and B-Class workstations.
Details
- PA-RISC version 1.1e 32-bit architecture, single-processor, 2-way superscalar
- Three functional units
- 2 integer ALUs
- 1 Floating Point unit
- MAX-1 multimedia extensions for multimedia applications
- Prediction and buffers
- Instruction prefetch buffer moved from memory controller to L1 instruction cache, allowing prefetch hits without penalty
- Translation Lookaside Buffer (TLB): 96-entry unified instruction and data for virtual-to-physical memory address translations
- Block Translation Lookaside Buffer (BTLB): 8-entry for virtual-to-physical address rage translations
- 4-entry ILAB
- Caches
- L1 cache 64 KB/64 KB instruction and data on-chip, each two-way set associative, virtually indexed, cache line size of 32 Byte
- Caches have a 64-bit datapath to the execution units, 256-bit datapath to main memory
- L2 cache optional up to 8192 KB unified off-chip, write-through, direct mapped, physically indexed and physically tagged
- No hashing for both instruction and data caches
- Memory
- On-chip MIOC memory controller
- Either 64-bit or 128-bit datapath from execution units to the memory
- Bi-endian support
- GSC system interface implements GSC+, maximum clock 40 MHz; implemented from 33 MHz and 132 MB/s up to 40 MHz and 160 MB/s
- Up to 180 MHz frequency with 3.3 V core voltage
- 15.3×17.0 mm2 die, 9,200,000 FETs, 0.5µ, 4-layer metal CMOS14C, 464-pin ceramic PGA package
Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition or multiplication. Both units can handle branch operations.
Used in
- HP 9000 744, 745, 748 VME workstations
- HP 9000 A180, A180C servers
- HP 9000 B132L, B132L+, B160L, B180L+ workstations
- HP 9000 C132L, C160L workstations
- HP 9000 D220, D230, D320, D330 servers
- RDI PrecisionBook laptop
- Hitachi 3050RX 255, 355E, 365 workstations
- HP Agilent 16600A, 16700A, 16700B, 16702A and 16702B series logic analyzers
References
- PA7300LC ERS (External Reference Specification) (PDF, 716 KB) Hewlett-Packard Company (1996)
- The PA-7300LC: the first
System on a Chip
archive.org Tom Meyer (1996: Presentation for Microprocessor Forum 1995) - The PA 7300LC Microprocessor: A Highly Integrated System on a Chip (PDF, 50 KB) Terry W. Blanchard and Paul G. Tobin (June 1997: Hewlett-Packard Journal)