PA-RISC information - since 1999

PA-7300LC PA-RISC Processor

Overview

The PA-7300LC is an integrated, 32-bit PA-RISC processor, released in 1996 and used in many mid- to late-1990s integrated HP Visualize workstations. PA-7300LC was a close successor low-cost to the earlier, highly-integrated PA-7100LC CPU, with several enhancements:

  1. Large on-chip L1 caches, in contrast to the small L1 on-chip assist caches of the PA-7100LC and PA-7200
  2. Integrated L2 cache controller in the on-chip Memory and I/O Controller (MIOC)
  3. Improved bus interface with faster GSC+ bus variant for up to 160MB/s
  4. Faster memory interface
PA-7300LC die
PA-7300LC die, © HP

The contemporary process technologies made it finally possible for HP to include a large L1 cache on the CPU die, breaking a long-standing HP tradition of large and off-chip L1 caches.

PA-7300LC was the final 32-bit, PA-RISC version 1.1 processor after the high-performance PA-7200. The first HP 64-bit PA-RISC 2.0 processor, the PA-8000, was introduced in the same timeframe.

HP used the PA-7300LC processor to close the gap on lower price-point workstations at the bottom of its product lineup like A180 servers and B-Class workstations.

Processor details

Functional units

PA-7300LC is a 32-bit PA-RISC processor, implementing PA-RISC version 1.1c. It is single-processor only and two-way superscalar, so it can decode, dispatch and execute two instructions per cycle. As the PA-7100LC, only the first ALU can handle loads, stores and shifts which can only be paired with simple math operations, like integer addition or multiplication.

There are three integrated functional units in PA-7300LC: two Integer ALUs and one Floating Point unit (FPU) plus MAX-1 multimedia extensions for multimedia applications. The PA-7300LC CPU has a five-stage pipeline.

The Translation Lookaside Buffer (TLB) has 96 unified instruction and data entries and translates virtual-to-physical memory addresses, the Block Translation Lookaside Buffer (BTLB) with 8 entries translates pages.

Cache and memory

PA-7300LC processors have an on-chip L1 cache of 64 KB/64 KB instruction and data on-chip, each two-way set associative, virtually indexed, cache line size of 32 Byte. An optional L2 cache is off-chip with up to 8192 KB unified, write-through, direct mapped, physically indexed and physically tagged. There is no hashing for both instruction and data caches.

The memory and I/O controller (MIOC) is integrated in PA-7300LC onto the die, for direct DRAM memory and cache interface. Up to 3.75 GB memory is supported.

PA-7300LC moved the instruction prefetch buffer from memory controller to L1 instruction cache, allowing prefetch hits without penalty. The instruction lookaside buffer (ILAB) has four entries for bypassing instructions from MIOC to execution.

The PA-7300LC is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-7300LC processors were fabbed with up to 180 MHz clock speed, on 3.3V core voltage. They directly attach to the GSC+ main system bus with 32-bit from processor to graphics I/O devices, maximum clock 40 MHz with 160 MB/s Caches have a 64-bit datapath to the execution units, 256-bit datapath to main memory, memory has a 128-bit datapatch.

Physical

Fabricated by HP, PA-7300LC had a 15.3×17.0 mm² die with 9,200,000 transistors (FETs), fabbed in a 0.5µ, 4-layer HP CMOS14C process packaged in a 464-pin ceramic PGA.

Performance

HP PA-7300LC PA-RISC were performant low-cost microprocessors, on par with RISC and PC competition in 1996. At the same clock, PA-7300LC were slightly faster than Sun UltraSPARC (1995), Pentium Pro (1995) and PowerPC 604e (1996), in SPEC95 scores. Floating point results were weaker.

In comparison, MIPS R10000 (1996) and Pentium II (1997) processors beat PA-7300LC only at higher clock rates. The 64-bit PA-8000 follow-on PA-RISC processors from HP were about 30% faster, at the same clock.

PA-7300LC were significantly faster than their PA-7100LC predecessors and slightly faster than the more expensive but much more expandable PA-7200.

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Used in

PA-7300LC processors were used in a few late-1990s HP 9000 workstations and servers, when technical computing was already moving to 64-bit. Systems with PA-7300LC were a medium-performance low-cost option for HP 9000 Unix customers.

Documentation

  1. PA7300LC ERS (External Reference Specification) (PDF, 716 KB) Hewlett-Packard Company (1996)
  2. The PA-7300LC: the first System on a Chip archive.org Tom Meyer (1996: Presentation for Microprocessor Forum 1995)
  3. The PA 7300LC Microprocessor: A Highly Integrated System on a Chip (PDF, 50 KB) Terry W. Blanchard and Paul G. Tobin (June 1997: Hewlett-Packard Journal)
  4. PA7300LC Integrates Cache for Cost/Performance, HP Technical Computing (1997) archive.org
  5. INTEGRATED PA-7300LC POWERS HP MIDRANGE, MICROPROCESSOR REPORT (VOL.9 NO.15, 1995, HP repring) archive.org

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