PA-RISC information - since 1999

PA-RISC Processors

PA-7300LC (PCX-L2) processor


The PA-7300LC is an integrated, low-cost PA-RISC 32-bit processor, released in mid-1996. While being a close successor to the earlier PA-7100LC, it has several enhancements:

  1. Large on-chip L1 caches, in contrast to the small assist caches of the PA-7100LC and PA-7200.
  2. Integrated L2 cache controller in the MIOC.
  3. Improved bus interface with faster GSC bus variant.
  4. Faster memory interface.

The then current process technologies made it possible to include a large L1 cache on the CPU die, breaking a long-standing HP tradition of large off-chip L1 caches. The PA-7300LC was the final 32-bit, PA-RISC version 1.1 CPU, later workstations and servers used 64-bit PA-RISC 2.0 processors, such as the PA-8000, being introduced in the same timeframe.


Only one of the two integer ALUs is able to handle loads, stores and shifts, these operations can only be paired with simple math operations, like integer addition o multiplication. Both units can handle branch operations.

Used in


  1. PA7300LC ERS (External Reference Specification) (PDF, 716 KB) Hewlett-Packard Company (1996)
  2. The PA-7300LC: the first System on a Chip ( mirror) Tom Meyer (1996: Presentation for Microprocessor Forum 1995)
  3. The PA 7300LC Microprocessor: A Highly Integrated System on a Chip (PDF, 50 KB) Terry W. Blanchard and Paul G. Tobin (June 1997: Hewlett-Packard Journal)

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