PA-8000 PA-RISC Processor

PA-8000 was the first 64-bit PA-RISC 2.0 processor by HP, released in 1996. It was four-way superscalar, had out-of-order execution capabilities, 64-bit integer registers and functional units, and a flat 64-bit virtual address space, a first for PA-RISC. PA-8000 processors were used in 64-bit HP Visualize workstations and servers for Unix.

PA-8000 die
PA-8000 die, © HP 1998

PA-8000 processors had a completely redesigned core and microarchitecture with ten functional units, a large out-of-order dispatch window and (still) no on-chip caches. Other PA-8000 new features are fast TLB insert and memory prefetch instructions, support for variable sized pages, branch prediction hinting and new floating point units (FPMAC).

The key feature in PA-8000 and PA-RISC 2.0 processors is the Instruction Reorder Buffer (IRB) for out-of-order (OoO) execution, which performs instruction scheduling in hardware, independent of compiler or software. IRB can store up to 28 computation and 28 load/store instructions, tracks interdepencies between these instructions and allows execution as soon as ready.

All 64-bit PA-RISC processors until the final PA-8900 are based on the PA-8000 CPU core with higher clock, slight modifications and bigger caches. PA-8000 was followed by the 64-bit PA-8200 processor.

Processor details

Functional units

PA-8000 is a 64-bit PA-RISC processor that implements version 2.0 of PA-RISC architecture. It is multi-processor capable (SMP) and four-way superscalar, so it can decode, dispatch and execute four instructions per cycle.

Ten functional units provide the processing power in PA-8000: two Integer ALUs, two shift/merge units, two complete load/store pipelines, two Floating Point multiply/accumulate units, two Floating Point divide/square root units plus MAX-2 multimedia extensions (subword arithmetic) for multimedia applications.

PA-RISC 2.0 added an Instruction Reorder Buffer (IRB) to PA-8000 with 56-entry instruction queue/reorder buffer for instruction scheduling in hardware by the CPU for out-of-order (OoO) execution of instructions.

Translation Lookaside Buffer (TLB) has 96 entries, fully associative and dual-ported, and translates virtual-to-physical memory addresses, the Branch Target Address Cache (BTAC) has 32 entries and the Branch History Table (BHT) 256 entries.

Cache and memory

PA-8000 have large L1 off-chip caches, keeping a PA-RISC tradition. Main L1 cache is up to 1 MB instruction and 1 MB data, off-chip in synchronous 150 MHz 1 Mb SRAMs with one cycle latency. Apparently, the theoretical L1 maximum is 4MB/4MB. There is no L2 cache.

Memory and I/O controller (MIOC) for accessing the memory and main buses is off-chip. Main memory is supported up to 1 TB with 40-bit physical addresses.

PA-8000 is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-8000 processors were fabbed with up to 180 MHz clock speed at 3.3 V core voltage. They attach to Runway bus, 64-bit, 120 MHz, 960 MB/s peak bandwidth.

PA-8000 support glueless multiprocessing (four-way SMP) on the same Runway bus.

Physical

Fabricated by HP, PA-8000 have a 17.7×19.1 mm² die with 3,800,000 transistors (FETs), fabbed in a 0.5µ, 5-layer metal HP CMOS process and packaged in 1,085-pin flip-chip LGA.

Performance

PA-8000 performance
PA-8000 performance, © HP 1996

HP PA-8000 PA-RISC were very fast 64-bit microprocessors in 1996, above their RISC competition for technical computing. PA-8000 were faster than IBM PowerPC 604e (1996), Pentium Pro (1995), Pentium II (1997) and MIPS R10000 (1996) at similar to higher clockspeeds, and exceptionally stronger in floating point.

PA-8000 were almost par with Pentium II (1997) and UltraSPARC IIi (1997) sold at significantly higher clocks, but again much faster in floating point – important for CAD/CAE and analysis software. They were more than ⅓ faster at the same clock than 32-bit PA-7200 and PA-7300LC predecessors and much faster in FP.

Used in

PA-8000 processors were used by many late-1990s HP Visualize Unix workstations and HP 9000 servers after HP switched to 64-bit computing.

Documentation

  1. Advanced Performance features of the 64-bit PA-8000 archive.org Doug Hunt (1995: IEEE CompCon 5)
  2. PA-8000 Combines Complexity and Speed archive.org Linley Gwennap (1994: Microprocessor Report, Volume 8 Number 15)
  3. Four-Way Superscalar PA-RISC Processors (.pdf) Anne P. Scott et al (August 1997: Hewlett-Packard Journal)
  4. The HP PA-8000 RISC CPU A High Performance Out-of-Order Processor, Ashok Kumar (August 1996: IEEE Hot Chips VIII) archive.org
  5. PA-8000 Mid-Range and High-End Systems, HP Technical Computing (1997) archive.org
  6. The HP PA-8000 RISC CPU presentation, Ashok Kumar, HP (1996: IEEE Hot Chips VIII conference)
  7. The HP PA-8000 RISC CPU, Ashok Kumar, HP (1997 IEEE Micro) semantic scholar

up