PA-RISC information - since 1999

PA-RISC Processors

PA-8000 (PCX-U) processor


The PA-8000 is the first 64-bit PA-RISC 2.0 processor, and included out-of-order execution capabilities for the first time. It was released in 1996, in parallel to the 32-bit low-cost PA-7300LC processor. The PA-800 had four integer, four floating-point and dual load/store units, a large OoO dispatch window and no on-chip caches. It was the first chip to implement 64-bit PA-RISC 2.0 architecture to support 64-bit computing, which included 64-bit wide integer registers and functional units like ALU and a flat virtual address space of 64-bit. Other extensions in the PA-8000 included fast TLB insert instructions, memory prefetch instructions, support for variable sized pages, branch prediction hinting and new floating point units (FPMAC).

A key design feature of the PA-8000 and all following PA-RISC 2.0 processors was the IRB, the Instruction Reorder Buffer, which enables the processor to perform its own instruction scheduling in hardware, independent of compiler or software technologies. The IRB is the key part for the out-of-order capabilities of the PA-8000, and can store up to 28 computation and 28 load/store instructions, tracks interdepencies between these instructions and allows execution as soon as they are ready.

All later PA-8x00 processors up to the PA-8900 include slightly modified PA-8000 cores with only slight extensions plus later much bigger caches.


Used in


  1. Advanced Performance features of the 64-bit PA-8000 ( mirror) Doug Hunt (1995: IEEE CompCon 5)
  2. PA-8000 Combines Complexity and Speed ( mirror) Linley Gwennap (1994: Microprocessor Report, Volume 8 Number 15)
  3. Four-Way Superscalar PA-RISC Processors (.pdf) Anne P. Scott et al (August 1997: Hewlett-Packard Journal)
  4. The HP PA-8000 RISC CPU A High Performance Out-of-Order Processor (.pdf) [link gone] Ashok Kumar (August 1996: IEEE Hot Chips VIII)

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