PA-RISC Processors

PA-8200 (PCX-U+) processor

Overview

The PA-8200 is a 64-bit PA-RISC processor from HP that extended the original 64-bit PA-8000 soon after its release. Several aspects of the PA-8000 were improved with the PA-8200, released in 1997: branch prediction, TLB miss rates and cache sizes.

The PA-8200 should offer improved performace, compatibility with existing applications and short time to market. The availability of new 4 Mb SRAMs with faster access times allowed for increased CPU speed and larger caches. Smaller changes include an increase to the BHT and TLB as high benefit, low risk improvements.

Details

PA-RISC version 2.0, 64-bit architecture, multi-processor capable, 4-way superscalar
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
IRB: 56-entry instruction queue/reorder buffer
TLB: 120-entry fully-associative dual-ported
BTAC: 42-entry Branch Target Address Cache; BHT: 1024-entry Branch History Table
Cache 2 MB instruction and 2 MB data L1 off-chip, in synchronous 200 MHz 4 Mb SRAMs, one cycle latency
Caches are direct-mapped and dual-ported
Memory and I/O controllers are external
Bi-endian support
MAX-2 multimedia extensions subword arithmetic for multimedia applications
Runway system bus, 120 MHz, 64-bit, about 960 MB/s peak bandwidth
Up to 300 MHz, clock speed with 3.3 V core voltage
0.5µ, 5-layer metal CMOS

Used in

References

Four-Way Superscalar PA-RISC Processors (PDF, 190 KB) Anne P. Scott et al (August 1997: Hewlett-Packard Journal)
HP Pumps Up PA-8x00 Family (archive.org mirror) Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14). [Article reprint for cpu.hp.com]
HP's Latest PA-RISC Microprocessor Evolution Enables 50 Percent Application Performance Boost Hewlett-Packard (October 1996: HP press release). [Article mirror for hp.com]

↑ up