PA-8200 PA-RISC Processor

Overview

PA-8200 is a 64-bit PA-RISC processor from HP that extended the original 64-bit PA-8000 RISC design in 1997, soon after the original release. Several aspects of the PA-8000 were improved: branch prediction, TLB miss rates and cache sizes.

PA-8200 were designed to offer improved performace and compatibility with existing applications in a short time to market. The availability of new 4 Mb SRAMs with faster access times allowed for increased CPU speed and larger caches. Other high benefit, low risk improvements include an increase of BHT and TLB.

PA-8200 was followed by the PA-8500, released a year later in 1998, functionally similar but with large on-chip caches, breaking a long HP PA-RISC tradition.

Processor details

Functional units

PA-8200 is a 64-bit PA-RISC processor that implements version 2.0 of PA-RISC architecture. It is multi-processor capable (SMP) and four-way superscalar, so it can decode, dispatch and execute multiple instructions per cycle.

There are ten integrated functional units in the PA-8200: two Integer ALUs, two shift/merge units, two complete load/store pipelines, Floating Point multiply/accumulate units, two Floating Point divide/square root units plus plus MAX-2 multimedia extensions (subword arithmetic) for multimedia applications.

The Instruction Reorder Buffer (IRB) has an 56-entry instruction queue/reorder buffer for instruction scheduling in hardware by the CPU.

The Translation Lookaside Buffer (TLB) with 120 entries, fully associative and dual-ported, translates virtual-to-physical memory addresses, the Branch Target Address Cache (BTAC) has 32 entries, the Branch History Table (BHT) 1024 entries.

Cache and memory

PA-8200 have, in the PA-RISC tradition, large L1 off-chip caches. Main L1 cache is up to 2 MB instruction and 2 MB data, off-chip in synchronous 200 MHz 4 Mb SRAMs with one cycle latency. Caches are direct-mapped and dual-ported. No L2 cache.

Memory and I/O controller (MIOC) for accessing the memory and main buses is off-chip. Main memory is supported up to 1 TB with 40-bit physical addresses.

The PA-8200 is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-8200 processors were fabbed with up to 300 MHz clock speed at 3.3 V core voltage. They attach to Runway bus, 64-bit, 120 MHz, 960 MB/s peak bandwidth.

PA-8200 support glueless multiprocessing interface (SMP) on the same Runway bus.

Physical

Fabricated by HP, PA-8200 have a 17.7×19.6 mm² die with 4,500,000 transistors (FETs) in a 0.5µ, 5-layer metal CMOS14C process, packaged in 1,085-pin flip-chip LGA.

Performance

HP PA-8200 PA-RISC were very fast 64-bit microprocessors in 1997, above their RISC competition for technical computing. PA-8200 were significantly faster than Pentium II (1997), UltraSPARC IIi (1997) and Digital Alpha 21164A (1996) that had almost twice the clockspeed. Newer MIPS R10000 (1996/1997) with large caches were only slightly slower than PA-8200.

PA-8200 were only slightly faster than the 64-bit PA-8000, released a year earlier (1996) with slightly lower clock.

Used in

PA-8000 processors were used in few late-1990s HP Visualize technical workstations and some HP 9000 servers, for the top models and as an upgrade to PA-8000.

Documentation

Four-Way Superscalar PA-RISC Processors (PDF, 190 KB) Anne P. Scott et al (August 1997: Hewlett-Packard Journal) parisc linux
HP Pumps Up PA-8x00 Family Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14) archive.org
HP’s Latest PA-RISC Microprocessor Evolution Enables 50 Percent Application Performance Boost Hewlett-Packard (October 1996: HP press release) cpu shack
Microprocessor Forum 1997 Conference Proceedings, (October 1997: MicroDesign Resources) archive.org
- The Evolving RISC Landscape, Linley Gwennap (MDR), Microprocessor Forum 1997
- PA-8500: Scaling the PA-8200 with a Large Integrated Cache, Bill Queen (HP), Microprocessor Forum 1997

↑ up