PA-RISC Processors

PA-8500 (PCX-W) processor

Overview

The PA-8500 64-bit PA-RISC processor is the direct evolution of the PA-8000 and PA-8200 processors, leveraging their processing core but implementing large on-die L1 caches. Introduced in September 1998, the PA-8500 marked a break with the long-standing HP tradition of keeping large L1 caches off-chip. (The two years older PA-7300LC also included on-chip L1 caches, albeit much smaller). There were no other significant changes to the processing core, besides small increases to the TLB and BHT.

Details

PA-RISC version 2.0, 64-bit architecture, multi-processor capable, 4-way superscalar
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
IRB: 56-entry instruction queue/reorder buffer
TLB: 160-entry fully-associative dual-ported
BTAC: 32-entry Branch Target Address Cache; BHT: 2048-entry Branch History Table
Cache 0.5 MB instruction and 1 MB data L1 on-chip, each 4-way set associative
Memory up to 1 TB supported with 40-bit physical addresses
Memory and I/O controllers are external
Bi-endian support
MAX-2 multimedia extensions subword arithmetic for multimedia applications
Runway+ system bus, 125 MHz, 64-bit, DDR, about 2 GB/s peak bandwidth
Up to 300 MHz, clock speed with 3.3 V core voltage
21.3×22.0 mm² die, 140,000,000 FETs, 0.25µ (micron), 5-layer metal CMOS packaged in a 544-pin LGA package

Used in

HP 9000 A400-44 (rp2400), A500-44 (rp2450) servers
HP 9000 B1000, B2000 workstations
HP 9000 C360, C3000 workstations
HP 9000 J5000, J7000 workstations
HP 9000 L1000-36, L1000-44 (rp5400), L2000-36, L2000-44 (rp5450) servers
HP 9000 N4000-36, N4000-44 (rp7400) servers
HP 9000 V2500 mainframes
Stratus Continuum 419, 429, 616S, 616, 619, 629, 1219, 1229 mainframes

References

HP Pumps Up PA-8x00 Family (archive.org mirror): Linley Gwennap (October 1994: Microprocessor Report, Volume 10 Number 14). [Article reprint for vanished cpu.hp.com]
A 500 MHz 1.5 MByte Cache with On-Chip CPU (PDF, 141 KB): Jonathan Lachman and J. Michael Hill (1997: ISSCC).
PA-8500: The Continuing Evolution of the PA-8000 Family (archive.org mirror): Gregg Lesartre and Doug Hunt (1997: Proceedings of CompCon, IEEE CS Press). [Article reprint for vanished cpu.hp.com]

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