PA-RISC information - since 1999

PA-8600 PA-RISC Processor

Overview

The PA-8600 is an 64-bit HP PA-RISC processor from HP, released in 2000 and based on a modified PA-8500 (1998) in a new manufacturing process to achieve higher clock speeds. Released shortly after the PA-8500, the PA-8600 was offered by HP as direct upgrade path for many HP 9000 servers and workstations for up to 550 MHz clock speed, utilizing the newer HP Runway+ DDR bus.

PA-8600 are basically uptuned PA-8500 processors, rated for higher clock speeds and a modifed manufacturing process at Intel, HP’s fabrication partner for a while in the 2000s before switching to IBM with the enhanced PA-8700 RISC CPU.

Processor details

Functional units

PA-8600 is a 64-bit PA-RISC processor that implements version 2.0 of PA-RISC architecture. It is multi-processor capable (SMP) and four-way superscalar, so it can decode, dispatch and execute multiple instructions per cycle.

There are ten integrated functional units in the PA-8600: two Integer ALUs, two shift/merge units, two complete load/store pipelines, Floating Point multiply/accumulate units (FPMAC), two Floating Point divide/square root units plus plus MAX-2 multimedia extensions (subword arithmetic) for multimedia applications.

The Instruction Reorder Buffer (IRB) has an 56-entry instruction queue/reorder buffer for instruction scheduling in hardware by the CPU.

The Translation Lookaside Buffer (TLB) with 160 entries, fully associative and dual-ported, translates virtual-to-physical memory addresses, the Branch Target Address Cache (BTAC) has 32 entries, the Branch History Table (BHT) 2048 entries.

Cache and memory

PA-8600 have large L1 on-chip caches, like PA-8500 for the first time before. Main L1 cache is 0.5 MB instruction and 1 MB data, on-chip, each 4-way set associative, with quasi LRU replacement policy for instruction cache.

Memory and I/O controller (MIOC) for accessing the memory and main buses is off-chip. Main memory is supported up to 1 TB with 40-bit physical addresses.

The PA-8600 is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-8600 processors were fabbed with up to 550 MHz clock speed at 2.0 V core voltage. They attach to Runway DDR bus, 64-bit, 125 MHz, 2 GB/s peak bandwidth.

Physical

Fabricated by Intel, PA-8600 have a 21.3×22.0 mm² die with 140,000,000 transistors (FETs) in a 0.25µ, 5-layer metal CMOS process, packaged in 544 LGA.

Performance

HP PA-8600 PA-RISC were fast 64-bit microprocessors of the early millenium (2000) and followed the PA-8500 performance-wise with slightly higher frequencies. The PA-8600 were in the same ballpark as higher clocked UltraSPARC III (2001), Pentium III Xeon (1999) and faster than Digital Alpha 21264 (1998). Performance was even with IBM RS64-VI (2000) and MIPS R14000 (2001) RISC processors at similar clock, while the newer Digital Alpha 21364 (2001) was faster with higher frequencies.

PA-8600 was notably faster than the first Itanium Merced (2001) from HP and Intel at higher clockrates, which in turn were much stronger in floating point (50%).

Used in

PA-8600 processors were used in high-end HP Visualize workstations and HP rp servers of the very late 1990s and early 2000s.

Documentation

  1. PA-RISC 8x00 Family of Microprocessors with Focus on PA-8700, Whitepaper, Hewlett Packard, April 2000 archive.org
  2. HP UNVEILS PA-8600 CHIP DETAILS, Hewlett Packard, March 1999 archive.org
  3. A 600 MHz 64 b PA-RISC microprocessor, K.A. Hurd, 2000 IEEE International Solid-State Circuits Conference

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