PA-8700 PA-RISC Processor

PA-8700 die
PA-8700 die, © HP

PA-8700 is a 64-bit HP PA-RISC processor from HP, released in 2001 as a superscalar RISC CPU with out-of-order capabilities. The PA-8700 core is close to the original 64-bit PA-8000 from 1997 but integrated significant on-chip L1 cache (2.25 MB) and TLB (240) compared to the earlier PA-8600.

PA-8700 was the last conventional PA-RISC 2.0 processor before HP moved to dual-core PA-8800 and PA-8900. Released in 2001, PA-8700 were a stop-gap measure by HP for 64-bit HP Visualize workstations and servers while waiting for Itanium processor to ship – originally planned for 1999. As MPR put it, HP is developing a processor called the PA-8700 to extend its current RISC line, tiding over customers until Merced systems are available.

HP decided to quit the RISC game with their own PA-RISC processors already in the late-1990s: After years of building their own processors, IBM, HP, and others have been forced to watch as systems based on commodity Intel microprocessors have chipped away at their market. HP recognized the futility of continued resistance and threw in the towel.

PA-8700 were followed by dual-core PA-8800 processors, (almost) end of the line for PA-RISC in 2004. The 875 MHz version of PA-8700 was called PA-8700+, used in top-range 64-bit PA-RISC workstations and many servers of the early 2000s.

HP switched to a new manufacturing partner with brand-new process for PA-8700, from Intel to IBM fabrication using silicon-on-insulator (SOI) and 0.18µ dies. This helped increase the CPU clock speed to 875 MHz. At its time, PA-8700 was one of the largest commercial processors and one of the first manufactured in SoI.

Processor details

Functional units

PA-8700 is a 64-bit PA-RISC processor that implements version 2.0 of PA-RISC architecture. It is multi-processor capable (SMP) and four-way superscalar, so it can decode, dispatch and execute multiple instructions per cycle.

Ten functional units provide the processing power in PA-8000: two Integer ALUs, two shift/merge units, two complete load/store pipelines, two Floating Point multiply/accumulate units, two Floating Point divide/square root units plus MAX-2 multimedia extensions (subword arithmetic) for multimedia applications.

Out-of-order (OoO) execution of instructions is handled by the Instruction Reorder Buffer (IRB) with a 56-entry instruction queue per core for instruction scheduling in hardware.

The Translation Lookaside Buffer (TLB) with 240 entries, fully associative and dual-ported, translates virtual-to-physical memory addresses, the Branch Target Address Cache (BTAC) has 32 entries, the Branch History Table (BHT) 2048 entries.

Cache and memory

PA-8700 have very large L1 on-chip caches. Main L1 cache is 0.75 MB instruction and 1.5 MB data, on-chip, each 4-way set associative, with quasi LRU replacement policy for instruction and data cache and data pre-fetching capability

Memory and I/O controller (MIOC) for accessing the memory and main buses is off-chip. Main memory is supported up to 16 TB with 44-bit physical addresses.

The PA-8700 is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-8700 processors were fabbed with up to 750 MHz and 875 MHz (PA-8750+) clock speed at 1.5 V core voltage. They attach to Runway DDR bus, 64-bit, 125 MHz, 2 GB/s peak bandwidth.

Physical

Fabricated by IBM, PA-8700 have a 16.0×19.0 mm² die with 186,000,000 transistors (FETs), produced in a 0.18µ 7-layer Silicon-on-Insulator CMOS-8S2SOI process from IBM, packaged in 544 LGA.

Performance

HP PA-8700 PA-RISC (2001) were still fast 64-bit CPUs in the early 2000s when competitors started increasing clock speeds for more performance. PA-8700 were ballpark as higher clocked as higher clocked UltraSPARC III (2001), Alpha 21364 (2001) and IBM POWER4+ (2003), faster than Pentium III Xeon (1999) and almost even with MIPS R14000 (2001).

The first Itanium Merced (2001) from HP and Intel was notably much slower than PA-8700 in integer but on par in floating point, while the second generation Itanium McKinley (2002) was faster with more than double the floating point performance.

Used in

PA-8700 processors were used in high-end HP Unix workstations and especially servers of the early 2000s.

Documentation

  1. A 900 MHz 2.25 MByte Cache with On Chip CPU (PDF, 119 KB) J. Michael Hill and Jonathan Lachman (2000: ISSCC) parisc linux
  2. PA-RISC 2.0 Architecture (.pdf) Hewlett-Packard Company (1995) parisc linux
  3. HP taps new foundry for PA-RISC processors, EE Times, August 2001
  4. PA-RISC 8x00 Family of Microprocessors with Focus on PA-8700, Whitepaper, Hewlett Packard, April 2000 archive.org
  5. PA-RISC: Betting the House and Winning, Hewlett Packard, 2000 archive.org
  6. HP REVEALS PA-8700 CHIP DETAILS, Hewlett Packard, 2000 archive.org
  7. Merced Slips to Mid-2000, Microprocessor Report (MPR), June 1998 (Vol 12 No 8) uci.edu
  8. Power4 Focuses on Memory Bandwidth, Microprocessor Report, October 1999 UMBC

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