PA-RISC Processors

PA-8700 (PCX-W2) processor

Overview

The PA-8700 processor is an 64-bit HP PA-RISC processor from HP, released in 2001 building on an enhanced PA-8500 core with several modifications. As with other PA-8x00 processors, the logic core is close to the original PA-8000 from 1997. The PA-8700 used significant larger on-chip L1 caches and TLB while switching to a new manufacturing process at IBM helped increase the clock speed. At its time it was one of the largest available commercial processors and one of the first manufactured in Silicon on Insulator (SoI). It is superscalar (4-way) and multi-processor (SMP) capable.

Details

PA-RISC version 2.0, 64-bit architecture, multi-processor capable, 4-way superscalar
Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
IRB: 56-entry instruction queue/reorder buffer
TLB: 240-entry fully-associative dual-ported
BTAC: 32-entry Branch Target Address Cache; BHT: 2048-entry Branch History Table
Cache 0.75 MB instruction and 1.5 MB data L1 on-chip, 4-way set associative, in independent 0.75 MB banks.
Memory up to 16 TB supported with 44-bit physical addresses
Memory and I/O controllers are external
Bi-endian support
MAX-2 multimedia extensions subword arithmetic for multimedia applications
Runway+ system bus, 125 MHz, 64-bit, DDR, about 2.0 GB/s peak bandwidth
Up to 750 MHz, 875 MHz on the PA-8700+ clock speed with 1.5 V core voltage
16.0×19.0 mm² die, 186,000,000 FETs, 0.18µ, 7-layer Silicon-on-Insulator CMOS packaged in a 544-pin LGA package

Used in

HP 9000 A400-6X (rp2430), A500-6X, A500-7X (rp2470), rp2405 servers
HP 9000 C3650, C3700, C3750 workstations
HP 9000 J6700 workstations
HP 9000 L1500-6X, L1500-7X, L1500-8X (rp5430), L3000-6X, L3000-7X, L3000-8X (rp5470) servers
HP 9000 N4000-6X, N4000-7X (rp7400) servers
HP 9000 N4000-6X, N4000-7X, N4000-8X (rp7405, rp7410) servers
HP 9000 Superdome mainframes (SD16000, SD32000, SD64000)

References

A 900 MHz 2.25 MByte Cache with On Chip CPU (PDF, 119 KB) J. Michael Hill and Jonathan Lachman (2000: ISSCC)
PA-RISC 2.0 Architecture (.pdf) Hewlett-Packard Company (1995)
HP taps new foundry for PA-RISC processors, EE Times, August 2001

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