PA-8900 PA-RISC Processor

PA-8900 is an improved PA-8800 dual-core 64-bit PA-RISC processor with increased cache (L2) and higher 1.1 GHz clock. It was released by HP in 2005, one year after the PA-8800 as the last PA-RISC processor in HP’s two-decades long RISC lineup. There were no more HP PA-RISC processors after the PA-8900 – HP c8000 workstations with dual PA-8900 CPUs were the pinnacle of PA-RISC workstation computing.

HP planned to transition its Unix computers to the Itanium (IA64) platform, a VLIW architecture called EPIC by HP that had been in joint development for more than a decade by HP and Intel. Alas, Itanium was never truly successful, shipped late and was often slower than RISC systems it was supposed to supersede.

When HP dropped its Itanium and Unix workstations in the mid-2000s, PA-8900-powered C8000 were some of the last and fastest HP-UX Unix workstations ever, shaded only by Itanium 2 zx6000 workstations. Information on the PA-8900 is limited, as was apparently its distribution in the market.

Processor details

Functional units

PA-8900 is a dual-core 64-bit PA-RISC processor that implements version 2.0 of PA-RISC architecture. It is multi-processor (SMP) and out-of-order capable, and four-way superscalar, so it can decode, dispatch and execute multiple instructions per cycle.

There are two seperate cores with each ten integrated functional units in the PA-8900: two Integer ALUs, two shift/merge units, two complete load/store pipelines, Floating Point multiply/accumulate units (FPMAC), two Floating Point divide/square root units and MAX-2 multimedia extensions (subword arithmetic) for multimedia applications.

PA-8900 has an Instruction Reorder Buffer (IRB) with 56 entries for instruction queueing/reordering per core, for instruction scheduling in hardware by the CPU for out-of-order (OoO) execution of instructions.

The Translation Lookaside Buffer (TLB) with 240 entries, fully associative and dual-ported, translates virtual-to-physical memory addresses, the Branch Target Address Cache (BTAC) has 32 entries, the Branch History Table (BHT) 2048 entries – all per core.

Cache and memory

PA-8900 have on-chip L1 caches and very large off-chip L2 caches. Main L1 cache is 0.75 MB instruction and 0.75 MB data on-chip, per core, each 4-way set associative. L2 cache is 64 MB off-chip with DDR-ESRAM chips, shared between the cores, L2 controller is on-chip.

Memory and I/O controller (MIOC) for accessing the memory and main buses is off-chip. Main memory is supported up to 16 TB with 44-bit physical addresses.

PA-8900 are bi-endian processors with support for little-endian and big-endian ordering.

Speed and buses

PA-8900 processors were produced with up to 1.1 GHz clock speed at 1.5 V core voltage, with higher clock speeds expected by the market but not released by HP. PA-8900 attach to Itanium processor but with 128-bit at 200 MHz for 6.4 GB/s bandwidth.

Physical

Fabricated by IBM, PA-8900 have a 23.6×15.5 mm² die with 317,000,000 transistors (FETs) in a 0.13µ 8-layer Silicon-on-Insulator CMOS process, a very large and complicated CPU for its time. IBM also fabbed the PA-8800 Mako predecessor, after HP switched from Intel.

Performance

HP PA-8900 PA-RISC were the pinnacle of 64-bit PA-RISC processor design and improved on the PA-8800 only slightly. No formal SPEC benchmark scores exist.

PA-8900 was a very fast RISC processor when released in 2005, faster at the same clockspeed than Alpha 21364 (2001), IBM POWER4+ (2003) and Itanium McKinley (2002). Contemporaries such as AMD Athlon XP (2002) and Intel Xeon (2003) had similar performance at much higher frequencies, AMD Opteron (2005) was faster.

Used in

PA-8900 processors were used in the final PA-RISC-powered HP Unix workstations and servers in the mid-2000s, when HP reserved Itanium processors for high-end models.

Documentation

up