PA-RISC information - since 1999

PA-8900 PA-RISC Processor

Overview

PA-8900 is a slightly tweaked PA-8800 PA-RISC 64-bit processor with increased cache (L2) and higher clock speed of 1.1 GHz. It was released by HP in 2005, only one year after PA-8800 as the last PA-RISC processor in RISC lineup. There were no more PA-RISC processors and products after PA-8900 and the HP c8000 workstation with dual PA-8900 was the pinnacle of PA-RISC workstation computing.

HP planned to transition its Unix computers to the Itanium (IA64) platform, a VLIW architecture called EPIC by HP, that had been in joint development for more than a decade by HP and Intel. Alas Itanium was never truly successful, shipped late and was often slower than the RISC systems it was supposed to supersede.

When HP dropped its line of Itanium and Unix workstations in the mid-2000s, PA-8900-powered C8000 were one of the last and quickest HP-UX Unix workstations, only shaded by Itanium 2 zx6000 workstations. Information on the PA-8900 is limited, as was apparently its distribution in the market.

Processor details

Functional units

PA-8900 is a dual-core 64-bit PA-RISC processor that implements version 2.0 of PA-RISC architecture. It is multi-processor capable (SMP) and four-way superscalar, so it can decode, dispatch and execute multiple instructions per cycle.

There are two seperate cores with each ten integrated functional units in the PA-8900: two Integer ALUs, two shift/merge units, two complete load/store pipelines, Floating Point multiply/accumulate units (FPMAC), two Floating Point divide/square root units plus plus MAX-2 multimedia extensions (subword arithmetic) for multimedia applications.

The Instruction Reorder Buffer (IRB) has an 56-entry instruction queue/reorder buffer per core for instruction scheduling in hardware by the CPU.

The Translation Lookaside Buffer (TLB) with 240 entries, fully associative and dual-ported, translates virtual-to-physical memory addresses, the Branch Target Address Cache (BTAC) has 32 entries, the Branch History Table (BHT) 2048 entries – all per core.

Cache and memory

PA-8900 have on-chip L1 caches and very large off-chip L2 caches. Main L1 cache is 0.75 MB instruction and 0.75 MB data on-chip, per core, each 4-way set associative. L2 cache is 64 MB off-chip with possibly DDR-ESRAM chips, shared between the cores, L2 controller is on-chip.

Memory and I/O controller (MIOC) for accessing the memory and main buses is off-chip. Main memory is supported up to 16 TB with 44-bit physical addresses.

The PA-8900 is bi-endian with support for little-endian and big-endian ordering.

Speed and buses

PA-8900 processors were fabbed with up to 1.1 GHz clock speed at 1.5 V core voltage. They attach to Itanium processor bus, 128-bit, 200 MHz, 6.4 GB/s bandwidth.

Physical

Fabricated possibly by IBM, PA-8900 have a 23.6×15.5 mm² die with 317,000,000 transistors (FETs) in a 0.13µ 8-layer Silicon-on-Insulator CMOS process.

Performance

HP PA-8900 PA-RISC were the pinnacle of 64-bit PA-RISC processor design, and improved on the PA-8800 only slightly. No formal SPEC benchmark scores exist.

PA-8900 was still a very fast RISC processor when released in 2005 and faster at the same clockspeed than Alpha 21364 (2001), IBM POWER4+ (2003) and Itanium McKinley (2002). Contemporaries such as AMD Athlon XP (2002) and Intel Xeon (2003) had similar performance at much higher frequencies, AMD Opteron (2005) was faster.

Used in

PA-8900 processors were used in the very final PA-RISC-powered HP Unix workstations and servers in the mid-2000s, when HP reserved Itanium processors for high-end models.

Documentation

  1. Overview of the HP 9000 rp3410-2, rp3440-4, rp4410-4, and rp4440-8 Servers (PDF, 700 KB), Hewlett-Packard (2005).
  2. HP Completes Its PA-RISC Road Map With Final Processor Upgrade, Information Week, June 2005
  3. HP delivers the last of the PA-RISC processors, Computer Business Review 2005
  4. HP moves out of pre-Itanium era , CNET 2005

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