PA-RISC information - since 1999

PA-RISC Processors

Early PA-RISC Designs

The first PA-RISC processors were designed be HP and used in mid to late-1980s in early HP 9000/800 servers and HP 3000 MPE/iX systems. These 32-bit RISC processors were mostly multi-chip implementations with separate chips forming the central processing unit, contrary to the mostly single-chip post-PA-7000 processors from the 1990s. Early PA-RISC CPUs were first based on TTL manufacturing, then NMOS-III and finally CMOS26B. An interesting aspect is their huge TLB size — from 2048 to 16384 entries while successors and competitors had sizes typically in the low to mid hundreds.

Early designs had clock speeds from 8 MHz up to 50 MHz in later versions, with 128 to 512 MB main memory. System designs were mostly based on the System Main Bus (SMB), as used in the early HP 9000 800 servers.

The exact naming is not always coherent as some sources refers to the processors as TS-1, NS-1, NS-2 and PCX while others call apparently the same processors PN-5, PN-7, PN-10, CMOS26b. Generally, sources and documentation on these pre-Internet PA-RISC processors is rather sparse to non-existent, adding to the slight unclearities.

TS-1 Processor

Overview

The TS-1 was the first PA-RISC production processor, introduced in 1986. It integrated version 1.0 of PA-RISC on six 8.4×11.3″ boards of TTL and was used in the first PA-RISC computers shipped by HP.

The TS-1 processor used in the HP 9000 840 is implented in several boards for processing units, processor pipeline, a 4096-entry TLB and 128  KB L1 cache, divided into 64  KB for each data and instruction. The TTL boards measure 8.4×11.3″ with SRAMs/PALs and about 150 ICs each. HP moved to NMOS with the next generation CPUs before settling with CMOS from the 90s on.

Details

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NS-1 Processor

Overview

The first implementation of PA-RISC in a NMOS fabrication process, NS-1, followed in 1987 shortly after the original TTL-based TS-1. The NS-1 processor is integrated on a single circuit board (two on 825 servers) with the CPU as single NMOS-III chip supplemented by external support chips.

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NS-2 Processor

Overview

The final NMOS PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 introduced in 1989-90 with from three to five stages increased pipeline, new TLB and cache controllers and significantly larger caches and TLB. The NS-2 is implemented on one circuit board with the CPU as a single NMOS-III and seven other VLSI chips. The bus structure connecting these chips was updated and simplified, with the CPU having private connections to the cache and TLB controllers, for which the NS-1 CPU had to use the shared cache bus.

Details

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PCX (CMOS26B) Processor

Overview

The last PA-RISC 1.0 design was the PCX, introduced 1990 and the first PA-RISC processor fabricated in a CMOS process. It implemented the NS-1/NS-2 design and several of the processor functions previously supplied on external VLSI chips onto a single CPU chip. The PCX was also supplemented by external support chips, including three cache multiplexers, the SPI main bus to processor interface, an floating point coprocessor and two FP chips for MUL/DIV and ADD/SUB. The successor to the PCX was the PA-RISC 1.1 PCX-S or PA-7000 processor, which integrated most processor logic minus the FPU onto a single die/chip

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Some sources mention a CS-1 PA-RISC 1.0 processor — CS would point to CMOS design but the performance figures and diagrams do not really match up with the CMOS26B/PCX described here.

Also, some other sources point to a (prototyped?) evolution of the last PA-RISC 1.0 CPU in CMOS – with up to 60 MHz (90 MHz), 4 MB L1 cache and PMB interface in a 408-pin PGA with 1.4×1.4cm die and 479k transistors – which in turn is eerily close to the PA-7000 processor.)

References

  1. Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture (January 1988: Software Research Northwest Inc.)
  2. Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal)
  3. HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008 at hpmuseum.net)
  4. HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008 at hpmuseum.net)
  5. HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008 at hpmuseum.net)
  6. New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com)
  7. HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008 at hpmuseum.net)
  8. A 30 MIPS VLSI CPU, Brian D. Boschma et al (ISSCC 89: February 1989)
  9. A CMOS RISC CPU designed for sustained high performance on large applications, J. Lotz et al (IEEE Journal of Solid-State Circuits October 1990)
  10. A 90 MHz CMOS RISC CPU designed for sustained performance, D. Tanksalvala et al (1990 37th IEEE International Conference on Solid-State Circuits)
  11. HP systems & vlsi technology division: pa-risc abstracts (archive.org mirror), Hewlett-Packard Company (2002: mirror accessed January 2024)

Pictures © Hewlett Packard, scans from product brochures, from hpmuseum.net and 1000bit.it

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