PA-RISC Processors
Early PA-RISC Designs
The first PA-RISC processors were designed be HP and used in mid to late-1980s in early HP 9000/800 servers and HP 3000 MPE/iX systems. These 32-bit RISC processors were mostly multi-chip implementations with separate chips forming the central processing unit, contrary to the mostly single-chip post-PA-7000 processors from the 1990s. Early PA-RISC CPUs were first based on TTL manufacturing, then NMOS-III and finally CMOS26B. An interesting aspect is their huge TLB size — from 2048 to 16384 entries while successors and competitors had sizes typically in the low to mid hundreds.
Early designs had clock speeds from 8 MHz up to 50 MHz in later versions, with 128 to 512 MB main memory. System designs were mostly based on the System Main Bus (SMB), as used in the early HP 9000 800 servers.
The exact naming is not always coherent as some sources refers to the processors as
TS-1, NS-1, NS-2 and PCX while others call apparently the same processors PN-5, PN-7, PN-10, CMOS26b.
Generally, sources and documentation on these pre-Internet
PA-RISC processors is rather sparse to non-existent, adding to the slight unclearities.
TS-1 Processor
Overview
The TS-1 was the first PA-RISC production processor, introduced in 1986. It integrated version 1.0 of PA-RISC on six 8.4×11.3″ boards of TTL and was used in the first PA-RISC computers shipped by HP.
Details
- PA-RISC version 1.0 32-bit, three-stage pipeline
- The CPU consists of six separate boards:
- I-unit Instruction Unit
- Register File Board, contains general and control registers
- E-unit Execution Unit
- TLB translation lookaside buffer with 4096 entries for 2 KB pages
- Cache controller with split instruction and data caches of 64 KB each
- FPC floating-point coprocessor, handles FP operations parallel to the CPU/ALU (ADD/MUL/DIV chip was taken over from HP 9000/550 FOCUS)
- TLB off-chip, direct-mapped, 4096 entries
- Cache 128 KB offchip L1 direct-mapped/one-way associative
- Physical address space of 27-bit, 128 MB main memory could be addressed
- Clock speed 8 MHz
- Six or five printed circuit boards, implemented in FAST TTL and 25ns/35ns SRAMs/PALs, with each about 150 ICs
Used in
- HP 9000 840 servers, the first PA-RISC computers.
NS-1 Processor
Overview
The first implementation of PA-RISC in a NMOS fabrication process, NS-1, followed in 1987 shortly after the original TTL-based TS-1. The NS-1 processor is integrated on a single circuit board (two on 825 servers) with the CPU as single NMOS-III chip supplemented by external support chips.
Details
- PA-RISC version 1.0 32-bit, three-stage pipeline
- Single CPU with eight support VLSI chips
- SIU system interface unit attaches the CPU to the SMB main bus
- CCU cache controller units CCU0 and CCU1 attach to external cache
- TCU TLB controller unit attaches to the external TLB
- MIU math interface unit with three third-party FP chips ADD, MUL and DIV
- TLB off-chip with 2048 to 4096 entries
- L1 cache 16 KB to 128 KB, unified and off-chip
- Physical address space of 29-bit, 512 MB main memory could be addressed
- CPU attaches via System Main Bus SMB to memory and I/O controllers, 64-bit bus
- Clock speed 25-30 MHz
- One circuit board, two boards on HP 9000/825
- 144,000 FETs, implemented in NMOS-III 1.7µ in a 272-pin ceramic PGA package
Used in
- HP 9000 825, 835, 850 servers
NS-2 Processor
Overview
The final NMOS PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 introduced in 1989-90 with from three to five stages increased pipeline, new TLB and cache controllers and significantly larger caches and TLB. The NS-2 is implemented on one circuit board with the CPU as a single NMOS-III and seven other VLSI chips. The bus structure connecting these chips was updated and simplified, with the CPU having private connections to the cache and TLB controllers, for which the NS-1 CPU had to use the shared cache bus.
Details
- PA-RISC version 1.0 32-bit, five-stage pipeline
- CPU is a single chip with seven VLSI support chips
- SIU system interface unit, attaches the CPU to the SMB main bus
- CCU cache controller units ICCU and DCCU, attach to external cache chips
- TCU TLB controller unit, attaches to external TLB chips
- FPC floating point controller and two third-party FP chips ADD, MULTI
- TLB off-chip, 16384 entries
- Cache up to 1024 KB L1, split into instruction and data, off-chip
- Physical address space of 29-bit, 512 MB main memory could be addressed
- CPU attaches via System Main Bus SMB to memory and I/O controllers, synchronous, pipelined 64-bit bus
- Clock speed 27.5 or 30 MHz, power dissipation of 26W
- One circuit board, CPU implemented in NMOS-III, 183,000 FETs, 1.5µ NMOS-III, die size 14.0×14.0 mm2 die, packaged in 408-pin PGA
Used in
PCX (CMOS26B) Processor
Overview
The last PA-RISC 1.0 design was the PCX, introduced 1990 and the first PA-RISC processor fabricated in a CMOS process. It implemented the NS-1/NS-2 design and several of the processor functions previously supplied on external VLSI chips onto a single CPU chip. The PCX was also supplemented by external support chips, including three cache multiplexers, the SPI main bus to processor interface, an floating point coprocessor and two FP chips for MUL/DIV and ADD/SUB. The successor to the PCX was the PA-RISC 1.1 PCX-S or PA-7000 processor, which integrated most processor logic minus the FPU onto a single die/chip
- PA-RISC version 1.0 32-bit
- First multi-processor-capable PA-RISC CPU, up to four-way SMP
- Seven external supported chips
- External FPU (apparently ECL logic)
- TLB on-chip with 8192 entries
- Cache up to 1 MB L1, split into instruction and data, off-chip, asymmetrical 1:2, some systems used up to 4 MB (890)
- Physical address space of 29-bit, 512 MB main memory could be addressed
- CPU attaches via System Main Bus SMB to memory and I/O controllers, 64-bit bus
- Clock speed up to 50 MHz or 60 MHz (some sources mentioned 90 MHz)
- One circuit board, 196,000 FETs, 1.0µ (micron), implemented in three-level CMOS26B
- CPU is a single chip with seven VLSI support chips for memory/bus interfaces and I/O
Some sources mention a CS-1
PA-RISC 1.0 processor — CS would point to CMOS design but the
performance figures and diagrams do not really match up with the CMOS26B/PCX described here.
Also, some other sources point to a (prototyped?) evolution of the last PA-RISC 1.0 CPU in CMOS – with up to 60 MHz, 4 MB L1 cache and PMB interface.
References
- Wayne E. Holt (ed.), Beyond RISC! An Essential Guide to Hewlett-Packard Precision Architecture (January 1988: Software Research Northwest Inc.)
- Hardware Design of the First HP Precision Architecture Computers (PDF) David A. Fotland et al (March 1987: Hewlett-Packard Journal)
- HP 3000 Series 950 and HP 9000 Model 850S Family CE Handbook (PDF) Hewlett-Packard Company (October 1990. Accessed January 2008 at hpmuseum.net)
- HP 9000 Series 800 Model 825S Hardware Technical Data (PDF) Hewlett-Packard Company (September 1988. Accessed January 2008 at hpmuseum.net)
- HP 3000/925 and HP 9000/825/835 Computer Systems CE Handbook (PDF) Hewlett-Packard Company (May 1988. Accessed January 2008 at hpmuseum.net)
- New midrange members of the Hewlett-Packard Precision Architecture Computer Family Thomas O. Meyer et al (June 1989: Hewlett Packard Journal. Accessed January 2008 at findarticles.com)
- HP 9000 Series 800 Model 822S/832S Technical Data (PDF) Hewlett-Packard Company (1989. Accessed January 2008 at hpmuseum.net)
- A 30 MIPS VLSI CPU, Brian D. Boschma et al (ISSCC 89: February 1989)
Pictures © Hewlett Packard, scans from product brochures, from hpmuseum.net and 1000bit.it