PA-RISC Processors
Overview
The PA-RISC platform is based on HP RISC processors developed by HP in the 1980s and used in HP computers from the 1980s to the 2000s. There are three versions of PA-RISC architecture:
- PA-RISC 1.0 32-bit, implemented in early 1980s processors and used in first PA-RISC servers: NS-1, NS-2 and PCX, plus the TTL TS-1 and maybe others.
- PA-RISC 1.1 32-bit, used in popular HP 9000 servers and workstations from the late-1980s to 90s: PA‑7000 and PA‑7100 and integrated PA‑7100LC and PA‑7300LC.
- PA-RISC 2.0 64-bit, used in many 1990s/2000s HP computers: PA‑8000/PA‑8200 and the updated PA‑8500, PA‑8600 and PA‑8700 with large on-chip caches. PA‑8800 and PA‑8900 are dual-core, with the final PA‑9000 never implemented.
The following PA-RISC processors have been developed by HP since 1986.
| CPU | ISA | Year | Chips | Clock up to |
Cache max |
Bus | Scalar | SMP | Units |
|---|---|---|---|---|---|---|---|---|---|
| FOCUS | 32-bit FOCUS |
1982 | NMOS 5 chips |
18 MHz | 16 KB external |
Custom | yes | INT FPU |
|
| TS-1 | 32-bit PA 1.0 |
1986 | TTL 6 boards |
8 MHz | 128 KB external |
Custom | 1-way | INT FPU |
|
| NS-1 | 32-bit PA 1.0 |
1987 | NMOS CPU + 8 |
30 MHz | 128 KB external |
SMB | 1-way | INT FPU |
|
| PRISM Apollo |
32-bit PRISM |
1988 | CMOS 11 chips |
18 MHz | 196 KB external |
X-bus | 1-way | Yes | INT FP |
| NS-2 | 32-bit PA 1.0 |
1989 | NMOS CPU + 7 |
27.5 MHz | 1 MB external |
SMB | 1-way | Yes | INT FPU |
| PCX | 32-bit PA 1.0 |
1990 | CMOS CPU + 7 |
50 MHz | 1 MB external |
SMB | 1-way | Yes | INT FPU |
| PA‑7000 | 32-bit PA 1.1a |
1991 | CMOS CPU + 1 |
66 MHz | 512 KB external |
PBus/VSC | 1-way | INT FPU |
|
| PA‑7100 PA‑7150 |
32-bit PA 1.1b |
1992 | CMOS CPU + 1 |
125 MHz | 3 MB external |
PBus/VSC | 2-way | Yes | INT FP |
| PA‑7100LC | 32-bit PA 1.1c |
1994 | CMOS CPU/MIOC |
100 MHz | 1 KB 2 MB L2 external |
GSC | 2-way | 2 INT FP MAX-1 |
|
| PA‑7200 | 32-bit PA 1.1d |
1995 | CMOS CPU |
140 MHz | 2 KB 3 MB L2 external |
Runway | 2-way | Yes | 2 INT FP |
| PA‑7300LC | 32-bit PA 1.1e |
1996 | CMOS CPU/MIOC |
180 MHz | 128 KB on-chip 8 MB L2 external |
GSC | 2-way | 2 INT FP MAX-1 |
|
| PA‑8000 | 64-bit PA 2.0 |
1996 | CMOS CPU |
230 MHz | 2 MB external |
Runway | 4-way | Yes | 4 INT 4 FP 2 L/S MAX-2 |
| PA‑8200 | 64-bit PA 2.0 |
1997 | CMOS CPU |
300 MHz | 4 MB external |
Runway | 4-way | Yes | 4 INT 4 FP 2 L/S MAX-2 |
| PA‑8500 | 64-bit PA 2.0 |
1998 | CMOS CPU |
440 MHz | 1.5 MB on-chip |
Runway | 4-way | Yes | 4 INT 4 FP 2 L/S MAX-2 |
| PA‑8600 | 64-bit PA 2.0 |
2000 | CMOS CPU |
550 MHz | 1.5 MB on-chip |
Runway | 4-way | Yes | 4 INT 4 FP 2 L/S MAX-2 |
| PA‑8700 | 64-bit PA 2.0 |
2001 | CMOS CPU |
875 MHz | 2.25 MB on-chip |
Runway | 4-way | Yes | 4 INT 4 FP 2 L/S MAX-2 |
| PA‑8800 dual-core |
64-bit PA 2.0 |
2004 | CMOS CPU dual |
1 GHz | 2×1.5 MB on-chip 32 MB L2 external |
Itanium 2 | 2×4-way | Yes | 2 cores 4 INT 4 FP 2 L/S MAX-2 |
| PA‑8900 dual-core |
64-bit PA 2.0 |
2005 | CMOS CPU dual |
1.1 GHz | 2×1.5 MB on-chip 64 MB L2 external |
Itanium 2 | 2×4-way | Yes | 2 cores 4 INT 4 FP 2 L/S MAX-2 |
| PA‑9000 | 64-bit VLIW |
dropped | super-parallel |
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Several third-party PA-RISC CPUs were developed, some in the PRO consortium.
| CPU | ISA | Year | Clock | Cache | Bus | Scalar | Units | Controllers |
|---|---|---|---|---|---|---|---|---|
| Amiga Hombre | 32-bit PA 1.1 |
1995 | 125 MHz | ? | 64-bit | 1-way | INT | yes |
| Hitachi PA/50L |
32-bit PA 1.1 |
1993 | 33 MHz | 12 KB | ? | 1-way | INT FP |
|
| Hitachi PA/50M |
32-bit PA 1.1 |
1993 | 60 MHz | 12 KB | ? | 1-way | INT FP |
|
| Hitachi HARP-1 |
32-bit PA 1.1 |
1994 | 150 MHz | 24 KB 1 MB L2 |
? | 2-way | 2 INT FP (Vector) |
|
| Winbond W89K | 32-bit PA 1.1 |
1994 | 33/66 MHz | 4 KB | i486 | 1-way | INT | |
| Winbond W90210 W90215 |
32-bit PA 1.1 |
1997 | 33/66 MHz | 12 KB | i486 | 1-way | INT MAX-1 |
yes |
| Winbond W90220 W90221 |
32-bit PA 1.1 |
1999 | 150 MHz | 8 KB | i486 | 1-way | INT 1 DSP MAX-1 |
yes |
| Oki OP32 | 32-bit PA 1.1 |
1994 | 33 MHz | ? | ? | 1-way | INT | yes |