PA-RISC Processors
Apollo PRISM Processor
Overview
PRISM was a RISC processor developed by Apollo Computer Inc. during the 1980s and released in 1988. PRISM was the first commercial CPU architecture with a VLIW (Very Long Instruction Word) design and was implemented on CMOS on a processor board consisting of eleven VLSI chips at 20 MHz clock. For the time, PRISM was billed as one of the fastest RISC processors, and was able to support up two four CPUs in a single system (SMP).
The processors were used in Apollo's own Domain 10000 (DN10000) line of computers, with a PRISM II processor already being planned and designed.
After the acquisition by HP in 1989, the Apollo products were integrated into the HP line up, but the PRISM II processor dropped.
Still, in 1989 HP was communicating an upgraded PRISM processor (DN10000TX upgrade
) – with a streamlined architecture, higher clock, double computing power (from 22 to 44 MIPS), increased caches to be fabbed by HP’s Colorado ASIC factory in 1991 in 1.0µ.
PRISM was sometimes codenamed A88K (or a88k), not to be confused with the Motorola M88K 88000 RISC processors, after Apollo earlier used Motorola 68000 processors in its workstations. Parts of the PRISM architecture were later reused in PA-RISC, including the FPU.
Details
- Apollo PRISM RISC VLIW architecture, 32-bit
- Designed and used by Apollo Computers in 1988-89
- Clock speed 20 MHz (or 18.18 MHz)
- CPU is a single chip with seven VLSI chips
- FPU from BIT (Bipolar Integrated Technologies)
- CPU design consists of eleven VLSI chips:
- IP: The Integer processor for calculations, adresses and sequencing
- MMU: Memory Management Unit from Toshiba
- FPC: Floating Point Control decodes and executes FP instructions
- Two FRFs: Floating Point Register File
- CBA: CPU Bus Address unit for the address path to cache and X-bus
- Two CBDs: CPU Bus Data unit for the data path to cache and X-bus
- SCR: Scan and Clock Resource
- FP ALU: from Bipolar Integrated Technology (BIT)
- FP MUL: also from BIT
- Two 32-bit integer registers, 32 floating point registers
- Cache L1 128 KB instruction and 64 KB data off-chip
- Shared virtual memory multiprocessing
- Up to 720 MB main memory could be addressed in a single system
- CPU attaches via X-Bus to memory, I/O and graphics, 64-bit bus, 150 Mb/s data rate
- One circuit board, CPU implemented in nine chips in 1.5µ VLSI CMOS plus two bipolar FP chips
Used in
- Apollo Domain DN10000 workstations
- Apollo Domain DSP10000 servers
DN10000TX (second generation)
- Upgrade PRISM processor designed by/with HP in 1991
- Apparently never marketed or productized
- Processor integrated in eigth VLSI chips instead of eleven
- IPU: Custom integration of IP, MMU and FPC
- FPU: Bipolar B2130 floating point unit
- Two KRF: Floating point register file
- Two KBD: X-bus data handling
- KBA:X-bus address handling
- SCR: clocks and testing
- Caches increased to 512/512 KB L1 (Motorola SRAMs)
- 64-bit data path (two buses) to the caches
- TLBs 32-entry primary (PTB) and 16K entries secondary (STB)
Second generation
Floating Point processors (BIT B2130)- X-bus data backplane 64-bit
- Up to four-way SMP multi-processing
- Clock speed increased to 30 MHz
- Fabricated in HP’s 1.0µ VLSI technology
References
- The DN 10000TX: a new high-performance PRISM processor, COMPCON Spring ’91 Digest of Papers, 1991
- APOLLO COMPUTER LAUNCHES ITS 64-BIT PRISM RISC MACHINE, Tech Monitor archive, February 29, 1988
- WHY APOLLO COMPUTER RECKONS IT HAS OUTDONE SUN IN THE RISC STAKES, Tech Monitor archive, March 14, 1988
- Apollo CPUs, Apollo/DOMAIN Computers at zepa.net, 2003 (archive.org mirror from 20030201)
- HP unveils plan for new PRISM CPU, Hewlett Packard, Press Release October 1989 (1000bit.it archive)