Philips LIFE VLIW
Intel iWarp
CPU details
Intel iWarp architecture used a 32-bit RISC processor core with 96-bit LIW (large instruction word) decoder for parallel processing.
The iWarp CPU was a 12x12 mm² die.
Used in
Intel iWarp processors were used in iWarp node computers as part of larger, parallel multi-processor system of the early 1990s.
Benchmarks
Foo
| Processor | Speed | Platform | MIPS/FLOPS | SPEC92 int/fp |
|---|---|---|---|---|
| Intel iWarp | 20 MHz | 20/20 |
Documentation
- , () archive.org
- Sun’s MAJC and Intel’s IA-64 , Ars Technica (1999)
- Sun’s New Chip is Pure MAJC, HPC Wire (2000)
- MAJCTM: An Architecture for the New Millennium, Sun Microsystems (HOT CHIPS 1999)
- MAJC, Sun Microsystems (2000) archive.org
- A High Performance Microprocessor for Multimedia Computing, MAJC-5200, Sun Microsystems (2000) archive.org
- MAJC Documentation, Sun Microelectronics (2000) archive.org